#ifndef _PERF_SYS_H #define _PERF_SYS_H #include #include #include #include #include #include #include #if defined(__i386__) #define cpu_relax() asm volatile("rep; nop" ::: "memory"); #define CPUINFO_PROC {"model name"} #endif #if defined(__x86_64__) #define cpu_relax() asm volatile("rep; nop" ::: "memory"); #define CPUINFO_PROC {"model name"} #endif #ifdef __powerpc__ #define CPUINFO_PROC {"cpu"} #endif #ifdef __s390__ #define CPUINFO_PROC {"vendor_id"} #endif #ifdef __sh__ #define CPUINFO_PROC {"cpu type"} #endif #ifdef __hppa__ #define CPUINFO_PROC {"cpu"} #endif #ifdef __sparc__ #define CPUINFO_PROC {"cpu"} #endif #ifdef __alpha__ #define CPUINFO_PROC {"cpu model"} #endif #ifdef __ia64__ #define cpu_relax() asm volatile ("hint @pause" ::: "memory") #define CPUINFO_PROC {"model name"} #endif #ifdef __arm__ #define CPUINFO_PROC {"model name", "Processor"} #endif #ifdef __aarch64__ #define cpu_relax() asm volatile("yield" ::: "memory") #endif #ifdef __mips__ #define CPUINFO_PROC {"cpu model"} #endif #ifdef __arc__ #define CPUINFO_PROC {"Processor"} #endif #ifdef __metag__ #define CPUINFO_PROC {"CPU"} #endif #ifdef __xtensa__ #define CPUINFO_PROC {"core ID"} #endif #ifdef __tile__ #define cpu_relax() asm volatile ("mfspr zero, PASS" ::: "memory") #define CPUINFO_PROC {"model name"} #endif #ifndef cpu_relax #define cpu_relax() barrier() #endif static inline int sys_perf_event_open(struct perf_event_attr *attr, pid_t pid, int cpu, int group_fd, unsigned long flags) { int fd; fd = syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags); #ifdef HAVE_ATTR_TEST if (unlikely(test_attr__enabled)) test_attr__open(attr, pid, cpu, fd, group_fd, flags); #endif return fd; } #endif /* _PERF_SYS_H */ ecommitdiff
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authorJiri Slaby <jslaby@suse.cz>2017-01-18 14:29:21 +0100
committerIngo Molnar <mingo@kernel.org>2017-01-19 08:39:44 +0100
commitb5b46c4740aed1538544f0fa849c5b76c7823469 (patch)
tree125e7aced4835bad6f6a0c0d02d012f333caf922 /include/net/tc_act/tc_defact.h
parentfa19a769f82fb9a5ca000b83cacd13fcaeda51ac (diff)
objtool: Fix IRET's opcode
The IRET opcode is 0xcf according to the Intel manual and also to objdump of my vmlinux: 1ea8: 48 cf iretq Fix the opcode in arch_decode_instruction(). The previous value (0xc5) seems to correspond to LDS. Signed-off-by: Jiri Slaby <jslaby@suse.cz> Acked-by: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20170118132921.19319-1-jslaby@suse.cz Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'include/net/tc_act/tc_defact.h')