[ { "EventCode": "0x80", "Counter": "0,1", "UMask": "0x3", "EventName": "ICACHE.ACCESSES", "SampleAfterValue": "200000", "BriefDescription": "Instruction fetches." }, { "EventCode": "0x80", "Counter": "0,1", "UMask": "0x1", "EventName": "ICACHE.HIT", "SampleAfterValue": "200000", "BriefDescription": "Icache hit" }, { "EventCode": "0x80", "Counter": "0,1", "UMask": "0x2", "EventName": "ICACHE.MISSES", "SampleAfterValue": "200000", "BriefDescription": "Icache miss" }, { "EventCode": "0x86", "Counter": "0,1", "UMask": "0x1", "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", "SampleAfterValue": "2000000", "BriefDescription": "Cycles during which instruction fetches are stalled." }, { "EventCode": "0x87", "Counter": "0,1", "UMask": "0x1", "EventName": "DECODE_STALL.PFB_EMPTY", "SampleAfterValue": "2000000", "BriefDescription": "Decode stall due to PFB empty" }, { "EventCode": "0x87", "Counter": "0,1", "UMask": "0x2", "EventName": "DECODE_STALL.IQ_FULL", "SampleAfterValue": "2000000", "BriefDescription": "Decode stall due to IQ full" }, { "EventCode": "0xAA", "Counter": "0,1", "UMask": "0x1", "EventName": "MACRO_INSTS.NON_CISC_DECODED", "SampleAfterValue": "2000000", "BriefDescription": "Non-CISC nacro instructions decoded" }, { "EventCode": "0xAA", "Counter": "0,1", "UMask": "0x2", "EventName": "MACRO_INSTS.CISC_DECODED", "SampleAfterValue": "2000000", "BriefDescription": "CISC macro instructions decoded" }, { "EventCode": "0xAA", "Counter": "0,1", "UMask": "0x3", "EventName": "MACRO_INSTS.ALL_DECODED", "SampleAfterValue": "2000000", "BriefDescription": "All Instructions decoded" }, { "EventCode": "0xA9", "Counter": "0,1", "UMask": "0x1", "EventName": "UOPS.MS_CYCLES", "SampleAfterValue": "2000000", "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. ", "CounterMask": "1" } ]ion value='grep'>log msg
path: root/tools/spi/spidev_fdx.c
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