[
    {
        "EventCode": "0x8",
        "Counter": "0,1",
        "UMask": "0x7",
        "EventName": "DATA_TLB_MISSES.DTLB_MISS",
        "SampleAfterValue": "200000",
        "BriefDescription": "Memory accesses that missed the DTLB."
    },
    {
        "EventCode": "0x8",
        "Counter": "0,1",
        "UMask": "0x5",
        "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB misses due to load operations."
    },
    {
        "EventCode": "0x8",
        "Counter": "0,1",
        "UMask": "0x9",
        "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
        "SampleAfterValue": "200000",
        "BriefDescription": "L0 DTLB misses due to load operations."
    },
    {
        "EventCode": "0x8",
        "Counter": "0,1",
        "UMask": "0x6",
        "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB misses due to store operations."
    },
    {
        "EventCode": "0x8",
        "Counter": "0,1",
        "UMask": "0xa",
        "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
        "SampleAfterValue": "200000",
        "BriefDescription": "L0 DTLB misses due to store operations"
    },
    {
        "EventCode": "0xC",
        "Counter": "0,1",
        "UMask": "0x3",
        "EventName": "PAGE_WALKS.WALKS",
        "SampleAfterValue": "200000",
        "BriefDescription": "Number of page-walks executed."
    },
    {
        "EventCode": "0xC",
        "Counter": "0,1",
        "UMask": "0x3",
        "EventName": "PAGE_WALKS.CYCLES",
        "SampleAfterValue": "2000000",
        "BriefDescription": "Duration of page-walks in core cycles"
    },
    {
        "EventCode": "0xC",
        "Counter": "0,1",
        "UMask": "0x1",
        "EventName": "PAGE_WALKS.D_SIDE_WALKS",
        "SampleAfterValue": "200000",
        "BriefDescription": "Number of D-side only page walks"
    },
    {
        "EventCode": "0xC",
        "Counter": "0,1",
        "UMask": "0x1",
        "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
        "SampleAfterValue": "2000000",
        "BriefDescription": "Duration of D-side only page walks"
    },
    {
        "EventCode": "0xC",
        "Counter": "0,1",
        "UMask": "0x2",
        "EventName": "PAGE_WALKS.I_SIDE_WALKS",
        "SampleAfterValue": "200000",
        "BriefDescription": "Number of I-Side page walks"
    },
    {
        "EventCode": "0xC",
        "Counter": "0,1",
        "UMask": "0x2",
        "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
        "SampleAfterValue": "2000000",
        "BriefDescription": "Duration of I-Side page walks"
    },
    {
        "EventCode": "0x82",
        "Counter": "0,1",
        "UMask": "0x1",
        "EventName": "ITLB.HIT",
        "SampleAfterValue": "200000",
        "BriefDescription": "ITLB hits."
    },
    {
        "EventCode": "0x82",
        "Counter": "0,1",
        "UMask": "0x4",
        "EventName": "ITLB.FLUSH",
        "SampleAfterValue": "200000",
        "BriefDescription": "ITLB flushes."
    },
    {
        "PEBS": "2",
        "EventCode": "0x82",
        "Counter": "0,1",
        "UMask": "0x2",
        "EventName": "ITLB.MISSES",
        "SampleAfterValue": "200000",
        "BriefDescription": "ITLB misses."
    },
    {
        "PEBS": "1",
        "EventCode": "0xCB",
        "Counter": "0,1",
        "UMask": "0x4",
        "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
        "SampleAfterValue": "200000",
        "BriefDescription": "Retired loads that miss the DTLB (precise event)."
    }
]tion value='4'>4</option><option value='5'>5</option><option value='6'>6</option><option value='7'>7</option><option value='8'>8</option><option value='9'>9</option><option value='10'>10</option><option value='15'>15</option><option value='20'>20</option><option value='25'>25</option><option value='30'>30</option><option value='35'>35</option><option value='40'>40</option></select></td></tr><tr><td class='label'>space:</td><td class='ctrl'><select name='ignorews' onchange='this.form.submit();'><option value='0' selected='selected'>include</option><option value='1'>ignore</option></select></td></tr><tr><td class='label'>mode:</td><td class='ctrl'><select name='dt' onchange='this.form.submit();'><option value='0' selected='selected'>unified</option><option value='1'>ssdiff</option><option value='2'>stat only</option></select></td></tr><tr><td/><td class='ctrl'><noscript><input type='submit' value='reload'/></noscript></td></tr></table></form></div><table summary='commit info' class='commit-info'>
<tr><th>author</th><td>Sergei Shtylyov &lt;sergei.shtylyov@cogentembedded.com&gt;</td><td class='right'>2017-01-29 15:07:34 +0300</td></tr>
<tr><th>committer</th><td>David S. Miller &lt;davem@davemloft.net&gt;</td><td class='right'>2017-01-30 22:05:43 -0500</td></tr>
<tr><th>commit</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/include/soc/tegra/fuse.h?id=1a0bee6c1e788218fd1d141db320db970aace7f0'>1a0bee6c1e788218fd1d141db320db970aace7f0</a> (<a href='/cgit.cgi/linux/net-next.git/patch/include/soc/tegra/fuse.h?id=1a0bee6c1e788218fd1d141db320db970aace7f0'>patch</a>)</td></tr>
<tr><th>tree</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/tree/?id=1a0bee6c1e788218fd1d141db320db970aace7f0'>46c4116bc8ef4a7df718516a648597d9e21c15f1</a> /<a href='/cgit.cgi/linux/net-next.git/tree/include/soc/tegra/fuse.h?id=1a0bee6c1e788218fd1d141db320db970aace7f0'>include/soc/tegra/fuse.h</a></td></tr>
<tr><th>parent</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/include/soc/tegra/fuse.h?id=63c190429020a9701b42887ac22c28f287f1762f'>63c190429020a9701b42887ac22c28f287f1762f</a> (<a href='/cgit.cgi/linux/net-next.git/diff/include/soc/tegra/fuse.h?id=1a0bee6c1e788218fd1d141db320db970aace7f0&amp;id2=63c190429020a9701b42887ac22c28f287f1762f'>diff</a>)</td></tr></table>
<div class='commit-subject'>sh_eth: rename EESIPR bits</div><div class='commit-msg'>Since the  commit  b0ca2a21f769 ("sh_eth: Add support of SH7763 to sh_eth")
the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with
the *enum* declaring the EESR bits (interrupt status) WRT  bit naming  and
formatting. I'd like to restore the consistency by using EESIPR as the bit
name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the
bits according to the available  Renesas SH77{34|63} manuals; additionally,
reconstruct  couple names using  the EESR bit declaration above...

Signed-off-by: Sergei Shtylyov &lt;sergei.shtylyov@cogentembedded.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</div><div class='diffstat-header'><a href='/cgit.cgi/linux/net-next.git/diff/?id=1a0bee6c1e788218fd1d141db320db970aace7f0'>Diffstat</a> (limited to 'include/soc/tegra/fuse.h')</div><table summary='diffstat' class='diffstat'>