[ { "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", "EventCode": "0x5C", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "CPL_CYCLES.RING0", "SampleAfterValue": "2000003", "BriefDescription": "Unhalted core cycles when the thread is in ring 0", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", "EventCode": "0x5C", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "CPL_CYCLES.RING123", "SampleAfterValue": "2000003", "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", "EventCode": "0x5C", "Counter": "0,1,2,3", "UMask": "0x1", "EdgeDetect": "1", "EventName": "CPL_CYCLES.RING0_TRANS", "SampleAfterValue": "100007", "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", "CounterMask": "1", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", "EventCode": "0x63", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "SampleAfterValue": "2000003", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", "CounterHTOff": "0,1,2,3,4,5,6,7" } ]b3cbea0946c67060e2d5bcb7499b0a6f6700fe'>commitdiff
path: root/tools/perf/ui/gtk
diff options
context:
space:
mode:
authorJerome Brunet <jbrunet@baylibre.com>2017-01-20 08:20:24 -0800
committerArnd Bergmann <arnd@arndb.de>2017-01-27 16:46:42 +0100
commitfeb3cbea0946c67060e2d5bcb7499b0a6f6700fe (patch)
tree4789978854a7fd97de08f4b77f220bcd9278417b /tools/perf/ui/gtk
parent7a308bb3016f57e5be11a677d15b821536419d36 (diff)
ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage
OdroidC2 GbE link breaks under heavy tx transfer. This happens even if the MAC does not enable Energy Efficient Ethernet (No Low Power state Idle on the Tx path). The problem seems to come from the phy Rx path, entering the LPI state. Disabling EEE advertisement on the phy prevent this feature to be negociated with the link partner and solve the issue. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/ui/gtk')