[ { "EventCode": "0x5C", "UMask": "0x1", "BriefDescription": "Unhalted core cycles when the thread is in ring 0", "Counter": "0,1,2,3", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", "SampleAfterValue": "2000003", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x5C", "UMask": "0x2", "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", "Counter": "0,1,2,3", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", "SampleAfterValue": "2000003", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EdgeDetect": "1", "EventCode": "0x5C", "UMask": "0x1", "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", "Counter": "0,1,2,3", "EventName": "CPL_CYCLES.RING0_TRANS", "CounterMask": "1", "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", "SampleAfterValue": "100007", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x63", "UMask": "0x1", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", "Counter": "0,1,2,3", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", "SampleAfterValue": "2000003", "CounterHTOff": "0,1,2,3,4,5,6,7" } ]eca944be9cd23dfc752'>commitdiff
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authorChristoph Hellwig <hch@lst.de>2017-01-30 13:15:41 +0100
committerBjorn Helgaas <bhelgaas@google.com>2017-02-02 10:35:46 -0600
commitdfef358bd1beb4e7b5c94eca944be9cd23dfc752 (patch)
treeb9a2afb38a4c2ac8ad31f49ec0d71fe9e5b1994c /tools/pcmcia
parent030305d69fc6963c16003f50d7e8d74b02d0a143 (diff)
PCI/MSI: Don't apply affinity if there aren't enough vectors left
Bart reported a problem wіth an out of bounds access in the low-level IRQ affinity code, which we root caused to the qla2xxx driver assigning all its MSI-X vectors to the pre and post vectors, and not having any left for the actually spread IRQs. Fix this issue by not asking for affinity assignment when there are no vectors to assign left. Fixes: 402723ad5c62 ("PCI/MSI: Provide pci_alloc_irq_vectors_affinity()") Link: https://lkml.kernel.org/r/1485359225.3093.3.camel@sandisk.com Reported-by: Bart Van Assche <bart.vanassche@sandisk.com> Tested-by: Bart Van Assche <bart.vanassche@sandisk.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'tools/pcmcia')