[
    {
        "EventCode": "0x5C",
        "UMask": "0x1",
        "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
        "Counter": "0,1,2,3",
        "EventName": "CPL_CYCLES.RING0",
        "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5C",
        "UMask": "0x2",
        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
        "Counter": "0,1,2,3",
        "EventName": "CPL_CYCLES.RING123",
        "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EdgeDetect": "1",
        "EventCode": "0x5C",
        "UMask": "0x1",
        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
        "Counter": "0,1,2,3",
        "EventName": "CPL_CYCLES.RING0_TRANS",
        "CounterMask": "1",
        "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
        "SampleAfterValue": "100007",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x63",
        "UMask": "0x1",
        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
        "Counter": "0,1,2,3",
        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
        "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    }
]</a></td><td class='form'><form class='right' method='get' action='/cgit.cgi/linux/net-next.git/log/sound/soc/qcom/lpass-cpu.c'>
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<div class='path'>path: <a href='/cgit.cgi/linux/net-next.git/log/?id=6e7bc478c9a006c701c14476ec9d389a484b4864'>root</a>/<a href='/cgit.cgi/linux/net-next.git/log/sound?id=6e7bc478c9a006c701c14476ec9d389a484b4864'>sound</a>/<a href='/cgit.cgi/linux/net-next.git/log/sound/soc?id=6e7bc478c9a006c701c14476ec9d389a484b4864'>soc</a>/<a href='/cgit.cgi/linux/net-next.git/log/sound/soc/qcom?id=6e7bc478c9a006c701c14476ec9d389a484b4864'>qcom</a>/<a href='/cgit.cgi/linux/net-next.git/log/sound/soc/qcom/lpass-cpu.c?id=6e7bc478c9a006c701c14476ec9d389a484b4864'>lpass-cpu.c</a></div><div class='content'><table class='list nowrap'><tr class='nohover'><th class='left'>Age</th><th class='left'>Commit message (<a href='/cgit.cgi/linux/net-next.git/log/sound/soc/qcom/lpass-cpu.c?id=6e7bc478c9a006c701c14476ec9d389a484b4864&amp;showmsg=1'>Expand</a>)</th><th class='left'>Author</th><th class='left'>Files</th><th class='left'>Lines</th></tr>
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<tr><th>author</th><td>Sakari Ailus &lt;sakari.ailus@linux.intel.com&gt;</td><td class='right'>2016-11-16 12:21:19 -0200</td></tr>
<tr><th>committer</th><td>Mauro Carvalho Chehab &lt;mchehab@s-opensource.com&gt;</td><td class='right'>2016-12-21 06:53:17 -0200</td></tr>
<tr><th>commit</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/net/core?id=9447082ae666fbf3adbe9c9152117daa31a8b737'>9447082ae666fbf3adbe9c9152117daa31a8b737</a> (<a href='/cgit.cgi/linux/net-next.git/patch/net/core?id=9447082ae666fbf3adbe9c9152117daa31a8b737'>patch</a>)</td></tr>
<tr><th>tree</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/tree/?id=9447082ae666fbf3adbe9c9152117daa31a8b737'>6838078a92f113c1097ebd7c46c51fb074f04251</a> /<a href='/cgit.cgi/linux/net-next.git/tree/net/core?id=9447082ae666fbf3adbe9c9152117daa31a8b737'>net/core</a></td></tr>
<tr><th>parent</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/net/core?id=d183e4efcae8d88a2f252e546978658ca6d273cc'>d183e4efcae8d88a2f252e546978658ca6d273cc</a> (<a href='/cgit.cgi/linux/net-next.git/diff/net/core?id=9447082ae666fbf3adbe9c9152117daa31a8b737&amp;id2=d183e4efcae8d88a2f252e546978658ca6d273cc'>diff</a>)</td></tr></table>
<div class='commit-subject'>[media] smiapp: Implement power-on and power-off sequences without runtime PM</div><div class='commit-msg'>Power on the sensor when the module is loaded and power it off when it is
removed.

Signed-off-by: Sakari Ailus &lt;sakari.ailus@linux.intel.com&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@s-opensource.com&gt;
</div><div class='diffstat-header'><a href='/cgit.cgi/linux/net-next.git/diff/?id=9447082ae666fbf3adbe9c9152117daa31a8b737'>Diffstat</a> (limited to 'net/core')</div><table summary='diffstat' class='diffstat'>