[ { "EventCode": "0xC1", "Counter": "0,1,2,3", "UMask": "0x8", "Errata": "HSD56, HSM57", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0xC1", "Counter": "0,1,2,3", "UMask": "0x10", "Errata": "HSD56, HSM57", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "Number of X87 FP assists due to output values.", "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "FP_ASSIST.X87_OUTPUT", "SampleAfterValue": "100003", "BriefDescription": "Number of X87 assists due to output value.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "Number of X87 FP assists due to input values.", "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "FP_ASSIST.X87_INPUT", "SampleAfterValue": "100003", "BriefDescription": "Number of X87 assists due to input value.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "Number of SIMD FP assists due to output values.", "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x8", "EventName": "FP_ASSIST.SIMD_OUTPUT", "SampleAfterValue": "100003", "BriefDescription": "Number of SIMD FP assists due to Output values", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "Number of SIMD FP assists due to input values.", "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "FP_ASSIST.SIMD_INPUT", "SampleAfterValue": "100003", "BriefDescription": "Number of SIMD FP assists due to input values", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "Cycles with any input/output SSE* or FP assists.", "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x1e", "EventName": "FP_ASSIST.ANY", "SampleAfterValue": "100003", "BriefDescription": "Cycles with any input/output SSE or FP assist", "CounterMask": "1", "CounterHTOff": "0,1,2,3" }, { "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.", "EventCode": "0xC6", "Counter": "0,1,2,3", "UMask": "0x7", "EventName": "AVX_INSTS.ALL", "SampleAfterValue": "2000003", "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.", "CounterHTOff": "0,1,2,3,4,5,6,7" } ] href='/cgit.cgi/linux/net-next.git/commit/tools/perf/scripts/python/stackcollapse.py?id=2ad5d52d42810bed95100a3d912679d8864421ec'>stackcollapse.py
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authorHelge Deller <deller@gmx.de>2017-01-28 11:52:02 +0100
committerHelge Deller <deller@gmx.de>2017-01-28 21:54:23 +0100
commit2ad5d52d42810bed95100a3d912679d8864421ec (patch)
tree7f93e2f906b1c86f5b76c0f4c0978d41a8a29861 /tools/perf/scripts/python/stackcollapse.py
parent83b5d1e3d3013dbf90645a5d07179d018c8243fa (diff)
parisc: Don't use BITS_PER_LONG in userspace-exported swab.h header
In swab.h the "#if BITS_PER_LONG > 32" breaks compiling userspace programs if BITS_PER_LONG is #defined by userspace with the sizeof() compiler builtin. Solve this problem by using __BITS_PER_LONG instead. Since we now #include asm/bitsperlong.h avoid further potential userspace pollution by moving the #define of SHIFT_PER_LONG to bitops.h which is not exported to userspace. This patch unbreaks compiling qemu on hppa/parisc. Signed-off-by: Helge Deller <deller@gmx.de> Cc: <stable@vger.kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')