[ { "EventCode": "0x17", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", "SampleAfterValue": "2000003", "BriefDescription": "Valid instructions written to IQ per cycle.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x5C", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "CPL_CYCLES.RING0", "SampleAfterValue": "2000003", "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x5C", "Counter": "0,1,2,3", "UMask": "0x1", "EdgeDetect": "1", "EventName": "CPL_CYCLES.RING0_TRANS", "SampleAfterValue": "100007", "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", "CounterMask": "1", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x5C", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "CPL_CYCLES.RING123", "SampleAfterValue": "2000003", "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x4E", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "HW_PRE_REQ.DL1_MISS", "SampleAfterValue": "2000003", "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x63", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "SampleAfterValue": "2000003", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", "CounterHTOff": "0,1,2,3,4,5,6,7" } ]thod='get' action='/cgit.cgi/linux/net-next.git/log/net/packet/diag.c'>
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authorJurij Smakov <jurij@wooyd.org>2017-01-30 15:41:36 -0600
committerKalle Valo <kvalo@codeaurora.org>2017-01-31 09:05:25 +0200
commit52f5631a4c056ad01682393be56d2be237e81610 (patch)
tree53d1ddd2c1b179c808df10b6ce731ad26aa9f31b /net/packet/diag.c
parent2b1d530cb3157f828fcaadd259613f59db3c6d1c (diff)
rtlwifi: rtl8192ce: Fix loading of incorrect firmware
In commit cf4747d7535a ("rtlwifi: Fix regression caused by commit d86e64768859, an error in the edit results in the wrong firmware being loaded for some models of the RTL8188/8192CE. In this condition, the connection suffered from high ping latency, slow transfer rates, and required higher signal strengths to work at all See https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=853073, https://bugzilla.opensuse.org/show_bug.cgi?id=1017471, and https://github.com/lwfinger/rtlwifi_new/issues/203 for descriptions of the problems. This patch fixes all of those problems. Fixes: cf4747d7535a ("rtlwifi: Fix regression caused by commit d86e64768859") Signed-off-by: Jurij Smakov <jurij@wooyd.org> Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Cc: Stable <stable@vger.kernel.org> # 4.9+ Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Diffstat (limited to 'net/packet/diag.c')