[
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "ICACHE.ACCESSES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts all instruction fetches, including uncacheable fetches."
},
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "200003",
"BriefDescription": "Counts all instruction fetches that hit the instruction cache."
},
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding."
},
{
"EventCode": "0xE7",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "MS_DECODED.MS_ENTRY",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of times the MSROM starts a flow of uops."
}
]ue='packet-loop-back'>packet-loop-back