[ { "PEBS": "1", "EventCode": "0x04", "Counter": "0,1", "UMask": "0x8", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", "SampleAfterValue": "200003", "BriefDescription": "Counts the number of load micro-ops retired that cause a DTLB miss", "Data_LA": "1" }, { "EventCode": "0x05", "Counter": "0,1", "UMask": "0x1", "EventName": "PAGE_WALKS.D_SIDE_WALKS", "SampleAfterValue": "100003", "BriefDescription": "Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted", "EdgeDetect": "1" }, { "EventCode": "0x05", "Counter": "0,1", "UMask": "0x1", "EventName": "PAGE_WALKS.D_SIDE_CYCLES", "SampleAfterValue": "200003", "BriefDescription": "Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included." }, { "EventCode": "0x05", "Counter": "0,1", "UMask": "0x2", "EventName": "PAGE_WALKS.I_SIDE_WALKS", "SampleAfterValue": "100003", "BriefDescription": "Counts the total I-side page walks that are completed.", "EdgeDetect": "1" }, { "PublicDescription": "This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress. ", "EventCode": "0x05", "Counter": "0,1", "UMask": "0x2", "EventName": "PAGE_WALKS.I_SIDE_CYCLES", "SampleAfterValue": "200003", "BriefDescription": "Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included." }, { "EventCode": "0x05", "Counter": "0,1", "UMask": "0x3", "EventName": "PAGE_WALKS.WALKS", "SampleAfterValue": "100003", "BriefDescription": "Counts the total page walks that are completed (I-side and D-side)", "EdgeDetect": "1" }, { "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.", "EventCode": "0x05", "Counter": "0,1", "UMask": "0x3", "EventName": "PAGE_WALKS.CYCLES", "SampleAfterValue": "200003", "BriefDescription": "Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included." } ]r'>author
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authorMarc Zyngier <marc.zyngier@arm.com>2017-01-17 16:00:48 +0000
committerThomas Gleixner <tglx@linutronix.de>2017-01-30 15:18:56 +0100
commit08d85f3ea99f1eeafc4e8507936190e86a16ee8c (patch)
tree410bb1acd0cd7dcfaad37ae7b63ff243b7fa4bee /sound/pci/lola/Makefile
parent566cf877a1fcb6d6dc0126b076aad062054c2637 (diff)
irqdomain: Avoid activating interrupts more than once
Since commit f3b0946d629c ("genirq/msi: Make sure PCI MSIs are activated early"), we can end-up activating a PCI/MSI twice (once at allocation time, and once at startup time). This is normally of no consequences, except that there is some HW out there that may misbehave if activate is used more than once (the GICv3 ITS, for example, uses the activate callback to issue the MAPVI command, and the architecture spec says that "If there is an existing mapping for the EventID-DeviceID combination, behavior is UNPREDICTABLE"). While this could be worked around in each individual driver, it may make more sense to tackle the issue at the core level. In order to avoid getting in that situation, let's have a per-interrupt flag to remember if we have already activated that interrupt or not. Fixes: f3b0946d629c ("genirq/msi: Make sure PCI MSIs are activated early") Reported-and-tested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: stable@vger.kernel.org Link: http://lkml.kernel.org/r/1484668848-24361-1-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'sound/pci/lola/Makefile')