[ { "EventCode": "0xE8", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", "BriefDescription": "Early Branch Prediciton Unit clears" }, { "EventCode": "0xE8", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", "BriefDescription": "Late Branch Prediction Unit clears" }, { "EventCode": "0xE5", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", "BriefDescription": "Branch prediction unit missed call or return" }, { "EventCode": "0xD5", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", "BriefDescription": "ES segment renames" }, { "EventCode": "0x6C", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", "BriefDescription": "I/O transactions" }, { "EventCode": "0x80", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", "BriefDescription": "L1I instruction fetch stall cycles" }, { "EventCode": "0x80", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", "BriefDescription": "L1I instruction fetch hits" }, { "EventCode": "0x80", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", "BriefDescription": "L1I instruction fetch misses" }, { "EventCode": "0x80", "Counter": "0,1,2,3", "UMask": "0x3", "EventName": "L1I.READS", "SampleAfterValue": "2000000", "BriefDescription": "L1I Instruction fetches" }, { "EventCode": "0x82", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", "BriefDescription": "Large ITLB hit" }, { "EventCode": "0x13", "Counter": "0,1,2,3", "UMask": "0x7", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", "BriefDescription": "All loads dispatched" }, { "EventCode": "0x13", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", "BriefDescription": "Loads dispatched from the MOB" }, { "EventCode": "0x13", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", "BriefDescription": "Loads dispatched that bypass the MOB" }, { "EventCode": "0x13", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", "BriefDescription": "Loads dispatched from stage 305" }, { "EventCode": "0x7", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", "BriefDescription": "False dependencies due to partial address aliasing" }, { "EventCode": "0xD2", "Counter": "0,1,2,3", "UMask": "0xf", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", "BriefDescription": "All RAT stall cycles" }, { "EventCode": "0xD2", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", "BriefDescription": "Flag stall cycles" }, { "EventCode": "0xD2", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", "BriefDescription": "Partial register stall cycles" }, { "EventCode": "0xD2", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", "BriefDescription": "ROB read port stalls cycles" }, { "EventCode": "0xD2", "Counter": "0,1,2,3", "UMask": "0x8", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", "BriefDescription": "Scoreboard stall cycles" }, { "EventCode": "0x4", "Counter": "0,1,2,3", "UMask": "0x7", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", "BriefDescription": "All Store buffer stall cycles" }, { "EventCode": "0xD4", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", "BriefDescription": "Segment rename stall cycles" }, { "EventCode": "0xB8", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "SNOOP_RESPONSE.HIT", "SampleAfterValue": "100000", "BriefDescription": "Thread responded HIT to snoop" }, { "EventCode": "0xB8", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "SNOOP_RESPONSE.HITE", "SampleAfterValue": "100000", "BriefDescription": "Thread responded HITE to snoop" }, { "EventCode": "0xB8", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "SNOOP_RESPONSE.HITM", "SampleAfterValue": "100000", "BriefDescription": "Thread responded HITM to snoop" }, { "EventCode": "0xF6", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", "BriefDescription": "Super Queue full stall cycles" } ]th>parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/usb/misc/yurex.c')