[ { "EventCode": "0xC1", "Counter": "0,1,2,3", "UMask": "0x8", "EventName": "OTHER_ASSISTS.AVX_STORE", "SampleAfterValue": "100003", "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0xC1", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0xC1", "Counter": "0,1,2,3", "UMask": "0x20", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "FP_ASSIST.X87_OUTPUT", "SampleAfterValue": "100003", "BriefDescription": "Number of X87 assists due to output value.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "FP_ASSIST.X87_INPUT", "SampleAfterValue": "100003", "BriefDescription": "Number of X87 assists due to input value.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x8", "EventName": "FP_ASSIST.SIMD_OUTPUT", "SampleAfterValue": "100003", "BriefDescription": "Number of SIMD FP assists due to Output values.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "FP_ASSIST.SIMD_INPUT", "SampleAfterValue": "100003", "BriefDescription": "Number of SIMD FP assists due to input values.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x10", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000003", "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x10", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", "SampleAfterValue": "2000003", "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x10", "Counter": "0,1,2,3", "UMask": "0x20", "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", "SampleAfterValue": "2000003", "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x10", "Counter": "0,1,2,3", "UMask": "0x40", "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", "SampleAfterValue": "2000003", "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x10", "Counter": "0,1,2,3", "UMask": "0x80", "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", "SampleAfterValue": "2000003", "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x11", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "SIMD_FP_256.PACKED_SINGLE", "SampleAfterValue": "2000003", "BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x11", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "SIMD_FP_256.PACKED_DOUBLE", "SampleAfterValue": "2000003", "BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x1e", "EventName": "FP_ASSIST.ANY", "SampleAfterValue": "100003", "BriefDescription": "Cycles with any input/output SSE or FP assist.", "CounterMask": "1", "CounterHTOff": "0,1,2,3" } ]id'>53d1ddd2c1b179c808df10b6ce731ad26aa9f31b /include/net/dst_metadata.h parent2b1d530cb3157f828fcaadd259613f59db3c6d1c (diff)
rtlwifi: rtl8192ce: Fix loading of incorrect firmware
In commit cf4747d7535a ("rtlwifi: Fix regression caused by commit d86e64768859, an error in the edit results in the wrong firmware being loaded for some models of the RTL8188/8192CE. In this condition, the connection suffered from high ping latency, slow transfer rates, and required higher signal strengths to work at all See https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=853073, https://bugzilla.opensuse.org/show_bug.cgi?id=1017471, and https://github.com/lwfinger/rtlwifi_new/issues/203 for descriptions of the problems. This patch fixes all of those problems. Fixes: cf4747d7535a ("rtlwifi: Fix regression caused by commit d86e64768859") Signed-off-by: Jurij Smakov <jurij@wooyd.org> Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Cc: Stable <stable@vger.kernel.org> # 4.9+ Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Diffstat (limited to 'include/net/dst_metadata.h')