[ { "EventCode": "0xAE", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "ITLB.ITLB_FLUSH", "SampleAfterValue": "100007", "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x4F", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", "BriefDescription": "Misses at all ITLB levels that cause page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.", "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "ITLB_MISSES.WALK_DURATION", "SampleAfterValue": "2000003", "BriefDescription": "Cycles when PMH is busy with page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x08", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", "BriefDescription": "Load misses in all DTLB levels that cause page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x08", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", "EventCode": "0x08", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "SampleAfterValue": "2000003", "BriefDescription": "Cycles when PMH is busy with page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.", "EventCode": "0x08", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "100003", "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", "BriefDescription": "Store misses in all DTLB levels that cause page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", "SampleAfterValue": "2000003", "BriefDescription": "Cycles when PMH is busy with page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0xBD", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "TLB_FLUSH.DTLB_THREAD", "SampleAfterValue": "100007", "BriefDescription": "DTLB flush attempts of the thread-specific entries.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0xBD", "Counter": "0,1,2,3", "UMask": "0x20", "EventName": "TLB_FLUSH.STLB_ANY", "SampleAfterValue": "100007", "BriefDescription": "STLB flush attempts.", "CounterHTOff": "0,1,2,3,4,5,6,7" } ]drivers/usb/gadget/function/f_hid.c?id=07cd12945551b63ecb1a349d50a6d69d1d6feb4a'>drivers/usb/gadget/function/f_hid.c parent7ce7d89f48834cefece7804d38fc5d85382edf77 (diff)
cgroup: don't online subsystems before cgroup_name/path() are operational
While refactoring cgroup creation, a5bca2152036 ("cgroup: factor out cgroup_create() out of cgroup_mkdir()") incorrectly onlined subsystems before the new cgroup is associated with it kernfs_node. This is fine for cgroup proper but cgroup_name/path() depend on the associated kernfs_node and if a subsystem makes the new cgroup_subsys_state visible, which they're allowed to after onlining, it can lead to NULL dereference. The current code performs cgroup creation and subsystem onlining in cgroup_create() and cgroup_mkdir() makes the cgroup and subsystems visible afterwards. There's no reason to online the subsystems early and we can simply drop cgroup_apply_control_enable() call from cgroup_create() so that the subsystems are onlined and made visible at the same time. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Konstantin Khlebnikov <khlebnikov@yandex-team.ru> Fixes: a5bca2152036 ("cgroup: factor out cgroup_create() out of cgroup_mkdir()") Cc: stable@vger.kernel.org # v4.6+
Diffstat (limited to 'drivers/usb/gadget/function/f_hid.c')