[ { "EventCode": "0xAE", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "ITLB.ITLB_FLUSH", "SampleAfterValue": "100007", "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x4F", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", "BriefDescription": "Misses at all ITLB levels that cause page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.", "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "ITLB_MISSES.WALK_DURATION", "SampleAfterValue": "2000003", "BriefDescription": "Cycles when PMH is busy with page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x08", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", "BriefDescription": "Load misses in all DTLB levels that cause page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x08", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", "EventCode": "0x08", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "SampleAfterValue": "2000003", "BriefDescription": "Cycles when PMH is busy with page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.", "EventCode": "0x08", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "100003", "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", "BriefDescription": "Store misses in all DTLB levels that cause page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", "SampleAfterValue": "2000003", "BriefDescription": "Cycles when PMH is busy with page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0xBD", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "TLB_FLUSH.DTLB_THREAD", "SampleAfterValue": "100007", "BriefDescription": "DTLB flush attempts of the thread-specific entries.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "EventCode": "0xBD", "Counter": "0,1,2,3", "UMask": "0x20", "EventName": "TLB_FLUSH.STLB_ANY", "SampleAfterValue": "100007", "BriefDescription": "STLB flush attempts.", "CounterHTOff": "0,1,2,3,4,5,6,7" } ]68&id2=0b3589be9b98994ce3d5aeca52445d1f5627c4ba'>diff)
perf/x86/intel/rapl: Make package handling more robust
The package management code in RAPL relies on package mapping being available before a CPU is started. This changed with: 9d85eb9119f4 ("x86/smpboot: Make logical package management more robust") because the ACPI/BIOS information turned out to be unreliable, but that left RAPL in broken state. This was not noticed because on a regular boot all CPUs are online before RAPL is initialized. A possible fix would be to reintroduce the mess which allocates a package data structure in CPU prepare and when it turns out to already exist in starting throw it away later in the CPU online callback. But that's a horrible hack and not required at all because RAPL becomes functional for perf only in the CPU online callback. That's correct because user space is not yet informed about the CPU being onlined, so nothing caan rely on RAPL being available on that particular CPU. Move the allocation to the CPU online callback and simplify the hotplug handling. At this point the package mapping is established and correct. This also adds a missing check for available package data in the event_init() function. Reported-by: Yasuaki Ishimatsu <yasu.isimatu@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sebastian Siewior <bigeasy@linutronix.de> Cc: Stephane Eranian <eranian@google.com> Cc: Vince Weaver <vincent.weaver@maine.edu> Fixes: 9d85eb9119f4 ("x86/smpboot: Make logical package management more robust") Link: http://lkml.kernel.org/r/20170131230141.212593966@linutronix.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'net/core/sock_diag.c')