[
    {
        "EventCode": "0x8",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "DTLB_LOAD_MISSES.ANY",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB load misses"
    },
    {
        "EventCode": "0x8",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB load miss caused by low part of address"
    },
    {
        "EventCode": "0x8",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
        "SampleAfterValue": "2000000",
        "BriefDescription": "DTLB second level hit"
    },
    {
        "EventCode": "0x8",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB load miss page walks complete"
    },
    {
        "EventCode": "0x8",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB load miss page walk cycles"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "DTLB_MISSES.ANY",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB misses"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x80",
        "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB miss large page walks"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "DTLB_MISSES.STLB_HIT",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB first level misses but second level hit"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "DTLB_MISSES.WALK_COMPLETED",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB miss page walks"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "DTLB_MISSES.WALK_CYCLES",
        "SampleAfterValue": "2000000",
        "BriefDescription": "DTLB miss page walk cycles"
    },
    {
        "EventCode": "0x4F",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "EPT.WALK_CYCLES",
        "SampleAfterValue": "2000000",
        "BriefDescription": "Extended Page Table walk cycles"
    },
    {
        "EventCode": "0xAE",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "ITLB_FLUSH",
        "SampleAfterValue": "2000000",
        "BriefDescription": "ITLB flushes"
    },
    {
        "PEBS": "1",
        "EventCode": "0xC8",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "ITLB_MISS_RETIRED",
        "SampleAfterValue": "200000",
        "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)"
    },
    {
        "EventCode": "0x85",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "ITLB_MISSES.ANY",
        "SampleAfterValue": "200000",
        "BriefDescription": "ITLB miss"
    },
    {
        "EventCode": "0x85",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "ITLB_MISSES.WALK_COMPLETED",
        "SampleAfterValue": "200000",
        "BriefDescription": "ITLB miss page walks"
    },
    {
        "EventCode": "0x85",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "ITLB_MISSES.WALK_CYCLES",
        "SampleAfterValue": "2000000",
        "BriefDescription": "ITLB miss page walk cycles"
    },
    {
        "PEBS": "1",
        "EventCode": "0xCB",
        "Counter": "0,1,2,3",
        "UMask": "0x80",
        "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
        "SampleAfterValue": "200000",
        "BriefDescription": "Retired loads that miss the DTLB (Precise Event)"
    },
    {
        "PEBS": "1",
        "EventCode": "0xC",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
        "SampleAfterValue": "200000",
        "BriefDescription": "Retired stores that miss the DTLB (Precise Event)"
    }
]on></select></td></tr><tr><td class='label'>mode:</td><td class='ctrl'><select name='dt' onchange='this.form.submit();'><option value='0' selected='selected'>unified</option><option value='1'>ssdiff</option><option value='2'>stat only</option></select></td></tr><tr><td/><td class='ctrl'><noscript><input type='submit' value='reload'/></noscript></td></tr></table></form></div><table summary='commit info' class='commit-info'>
<tr><th>author</th><td>Christoph Hellwig &lt;hch@lst.de&gt;</td><td class='right'>2017-01-30 13:15:41 +0100</td></tr>
<tr><th>committer</th><td>Bjorn Helgaas &lt;bhelgaas@google.com&gt;</td><td class='right'>2017-02-02 10:35:46 -0600</td></tr>
<tr><th>commit</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/include/dt-bindings/clock/renesas-cpg-mssr.h?id=dfef358bd1beb4e7b5c94eca944be9cd23dfc752'>dfef358bd1beb4e7b5c94eca944be9cd23dfc752</a> (<a href='/cgit.cgi/linux/net-next.git/patch/include/dt-bindings/clock/renesas-cpg-mssr.h?id=dfef358bd1beb4e7b5c94eca944be9cd23dfc752'>patch</a>)</td></tr>
<tr><th>tree</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/tree/?id=dfef358bd1beb4e7b5c94eca944be9cd23dfc752'>b9a2afb38a4c2ac8ad31f49ec0d71fe9e5b1994c</a> /<a href='/cgit.cgi/linux/net-next.git/tree/include/dt-bindings/clock/renesas-cpg-mssr.h?id=dfef358bd1beb4e7b5c94eca944be9cd23dfc752'>include/dt-bindings/clock/renesas-cpg-mssr.h</a></td></tr>
<tr><th>parent</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/include/dt-bindings/clock/renesas-cpg-mssr.h?id=030305d69fc6963c16003f50d7e8d74b02d0a143'>030305d69fc6963c16003f50d7e8d74b02d0a143</a> (<a href='/cgit.cgi/linux/net-next.git/diff/include/dt-bindings/clock/renesas-cpg-mssr.h?id=dfef358bd1beb4e7b5c94eca944be9cd23dfc752&amp;id2=030305d69fc6963c16003f50d7e8d74b02d0a143'>diff</a>)</td></tr></table>
<div class='commit-subject'>PCI/MSI: Don't apply affinity if there aren't enough vectors left</div><div class='commit-msg'>Bart reported a problem wіth an out of bounds access in the low-level IRQ
affinity code, which we root caused to the qla2xxx driver assigning all its
MSI-X vectors to the pre and post vectors, and not having any left for the
actually spread IRQs.

Fix this issue by not asking for affinity assignment when there are no
vectors to assign left.

Fixes: 402723ad5c62 ("PCI/MSI: Provide pci_alloc_irq_vectors_affinity()")
Link: https://lkml.kernel.org/r/1485359225.3093.3.camel@sandisk.com
Reported-by: Bart Van Assche &lt;bart.vanassche@sandisk.com&gt;
Tested-by: Bart Van Assche &lt;bart.vanassche@sandisk.com&gt;
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</div><div class='diffstat-header'><a href='/cgit.cgi/linux/net-next.git/diff/?id=dfef358bd1beb4e7b5c94eca944be9cd23dfc752'>Diffstat</a> (limited to 'include/dt-bindings/clock/renesas-cpg-mssr.h')</div><table summary='diffstat' class='diffstat'>