[
    {
        "EventCode": "0x8",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "DTLB_LOAD_MISSES.ANY",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB load misses"
    },
    {
        "EventCode": "0x8",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB load miss caused by low part of address"
    },
    {
        "EventCode": "0x8",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
        "SampleAfterValue": "2000000",
        "BriefDescription": "DTLB second level hit"
    },
    {
        "EventCode": "0x8",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB load miss page walks complete"
    },
    {
        "EventCode": "0x8",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB load miss page walk cycles"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "DTLB_MISSES.ANY",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB misses"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x80",
        "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB miss large page walks"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "DTLB_MISSES.STLB_HIT",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB first level misses but second level hit"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "DTLB_MISSES.WALK_COMPLETED",
        "SampleAfterValue": "200000",
        "BriefDescription": "DTLB miss page walks"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "DTLB_MISSES.WALK_CYCLES",
        "SampleAfterValue": "2000000",
        "BriefDescription": "DTLB miss page walk cycles"
    },
    {
        "EventCode": "0x4F",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "EPT.WALK_CYCLES",
        "SampleAfterValue": "2000000",
        "BriefDescription": "Extended Page Table walk cycles"
    },
    {
        "EventCode": "0xAE",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "ITLB_FLUSH",
        "SampleAfterValue": "2000000",
        "BriefDescription": "ITLB flushes"
    },
    {
        "PEBS": "1",
        "EventCode": "0xC8",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "ITLB_MISS_RETIRED",
        "SampleAfterValue": "200000",
        "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)"
    },
    {
        "EventCode": "0x85",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "ITLB_MISSES.ANY",
        "SampleAfterValue": "200000",
        "BriefDescription": "ITLB miss"
    },
    {
        "EventCode": "0x85",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "ITLB_MISSES.WALK_COMPLETED",
        "SampleAfterValue": "200000",
        "BriefDescription": "ITLB miss page walks"
    },
    {
        "EventCode": "0x85",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "ITLB_MISSES.WALK_CYCLES",
        "SampleAfterValue": "2000000",
        "BriefDescription": "ITLB miss page walk cycles"
    },
    {
        "PEBS": "1",
        "EventCode": "0xCB",
        "Counter": "0,1,2,3",
        "UMask": "0x80",
        "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
        "SampleAfterValue": "200000",
        "BriefDescription": "Retired loads that miss the DTLB (Precise Event)"
    },
    {
        "PEBS": "1",
        "EventCode": "0xC",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
        "SampleAfterValue": "200000",
        "BriefDescription": "Retired stores that miss the DTLB (Precise Event)"
    }
]able summary='commit info' class='commit-info'>
<tr><th>author</th><td>Bjorn Helgaas &lt;bhelgaas@google.com&gt;</td><td class='right'>2017-01-27 15:00:45 -0600</td></tr>
<tr><th>committer</th><td>Bjorn Helgaas &lt;bhelgaas@google.com&gt;</td><td class='right'>2017-01-27 15:00:45 -0600</td></tr>
<tr><th>commit</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/net/x25/x25_out.c?id=030305d69fc6963c16003f50d7e8d74b02d0a143'>030305d69fc6963c16003f50d7e8d74b02d0a143</a> (<a href='/cgit.cgi/linux/net-next.git/patch/net/x25/x25_out.c?id=030305d69fc6963c16003f50d7e8d74b02d0a143'>patch</a>)</td></tr>
<tr><th>tree</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/tree/?id=030305d69fc6963c16003f50d7e8d74b02d0a143'>363a4e34d199178769b7e7eeb26ea2620a55847b</a> /<a href='/cgit.cgi/linux/net-next.git/tree/net/x25/x25_out.c?id=030305d69fc6963c16003f50d7e8d74b02d0a143'>net/x25/x25_out.c</a></td></tr>
<tr><th>parent</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/net/x25/x25_out.c?id=4d191b1b63c209e37bf27938ef365244d3c41084'>4d191b1b63c209e37bf27938ef365244d3c41084</a> (<a href='/cgit.cgi/linux/net-next.git/diff/net/x25/x25_out.c?id=030305d69fc6963c16003f50d7e8d74b02d0a143&amp;id2=4d191b1b63c209e37bf27938ef365244d3c41084'>diff</a>)</td></tr></table>
<div class='commit-subject'>PCI/ASPM: Handle PCI-to-PCIe bridges as roots of PCIe hierarchies</div><div class='commit-msg'>In a struct pcie_link_state, link-&gt;root points to the pcie_link_state of
the root of the PCIe hierarchy.  For the topmost link, this points to
itself (link-&gt;root = link).  For others, we copy the pointer from the
parent (link-&gt;root = link-&gt;parent-&gt;root).

Previously we recognized that Root Ports originated PCIe hierarchies, but
we treated PCI/PCI-X to PCIe Bridges as being in the middle of the
hierarchy, and when we tried to copy the pointer from link-&gt;parent-&gt;root,
there was no parent, and we dereferenced a NULL pointer:

  BUG: unable to handle kernel NULL pointer dereference at 0000000000000090
  IP: [&lt;ffffffff9e424350&gt;] pcie_aspm_init_link_state+0x170/0x820

Recognize that PCI/PCI-X to PCIe Bridges originate PCIe hierarchies just
like Root Ports do, so link-&gt;root for these devices should also point to
itself.

Fixes: 51ebfc92b72b ("PCI: Enumerate switches below PCI-to-PCIe bridges")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=193411
Link: https://bugzilla.opensuse.org/show_bug.cgi?id=1022181
Tested-by: lists@ssl-mail.com
Tested-by: Jayachandran C. &lt;jnair@caviumnetworks.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: stable@vger.kernel.org	# v4.2+</div><div class='diffstat-header'><a href='/cgit.cgi/linux/net-next.git/diff/?id=030305d69fc6963c16003f50d7e8d74b02d0a143'>Diffstat</a> (limited to 'net/x25/x25_out.c')</div><table summary='diffstat' class='diffstat'>