[ { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", "BriefDescription": "DTLB load misses" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x20", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", "BriefDescription": "DTLB load miss caused by low part of address" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", "BriefDescription": "DTLB second level hit" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "DTLB load miss page walks complete" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", "BriefDescription": "DTLB load miss page walk cycles" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", "BriefDescription": "DTLB misses" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x80", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "DTLB miss large page walks" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", "BriefDescription": "DTLB first level misses but second level hit" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "DTLB miss page walks" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", "BriefDescription": "DTLB miss page walk cycles" }, { "EventCode": "0x4F", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", "BriefDescription": "Extended Page Table walk cycles" }, { "EventCode": "0xAE", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", "BriefDescription": "ITLB flushes" }, { "PEBS": "1", "EventCode": "0xC8", "Counter": "0,1,2,3", "UMask": "0x20", "EventName": "ITLB_MISS_RETIRED", "SampleAfterValue": "200000", "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", "BriefDescription": "ITLB miss" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "ITLB miss page walks" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", "BriefDescription": "ITLB miss page walk cycles" }, { "PEBS": "1", "EventCode": "0xCB", "Counter": "0,1,2,3", "UMask": "0x80", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", "SampleAfterValue": "200000", "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" }, { "PEBS": "1", "EventCode": "0xC", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", "SampleAfterValue": "200000", "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" } ]/tr>
author | Jiri Kosina <jkosina@suse.cz> | 2017-01-27 22:25:52 +0000 |
---|---|---|
committer | Ingo Molnar <mingo@kernel.org> | 2017-01-28 09:18:56 +0100 |
commit | bf29bddf0417a4783da3b24e8c9e017ac649326f (patch) | |
tree | 54a05a4883b73f80e4e1d8c4b15750aa01c39932 /sound/hda/ext | |
parent | 883af14e67e8b8702b5560aa64c888c0cd0bd66c (diff) |