[ { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", "BriefDescription": "DTLB load misses" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x80", "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "DTLB load miss large page walks" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x20", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", "BriefDescription": "DTLB load miss caused by low part of address" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", "BriefDescription": "DTLB second level hit" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "DTLB load miss page walks complete" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", "BriefDescription": "DTLB load miss page walk cycles" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", "BriefDescription": "DTLB misses" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x80", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "DTLB miss large page walks" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x20", "EventName": "DTLB_MISSES.PDE_MISS", "SampleAfterValue": "200000", "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE." }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", "BriefDescription": "DTLB first level misses but second level hit" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "DTLB miss page walks" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", "BriefDescription": "DTLB miss page walk cycles" }, { "EventCode": "0x4F", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", "BriefDescription": "Extended Page Table walk cycles" }, { "EventCode": "0xAE", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", "BriefDescription": "ITLB flushes" }, { "PEBS": "1", "EventCode": "0xC8", "Counter": "0,1,2,3", "UMask": "0x20", "EventName": "ITLB_MISS_RETIRED", "SampleAfterValue": "200000", "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", "BriefDescription": "ITLB miss" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x80", "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "ITLB miss large page walks" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "ITLB miss page walks" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", "BriefDescription": "ITLB miss page walk cycles" }, { "PEBS": "1", "EventCode": "0xCB", "Counter": "0,1,2,3", "UMask": "0x80", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", "SampleAfterValue": "200000", "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" }, { "PEBS": "1", "EventCode": "0xC", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", "SampleAfterValue": "200000", "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" } ]t;axboe@fb.com>2017-02-06 09:34:46 -0700 commiteeeefd41843218c55a8782a6920f044d9bf6207a (patch) treec342eac46626e62745aa8e1a982626efca8b121d /tools/virtio/ringtest/README parentc14024dbb156c8392908aaa822097d27c6af8ec8 (diff)
block: don't try Write Same from __blkdev_issue_zeroout
Write Same can return an error asynchronously if it turns out the underlying SCSI device does not support Write Same, which makes a proper fallback to other methods in __blkdev_issue_zeroout impossible. Thus only issue a Write Same from blkdev_issue_zeroout an don't try it at all from __blkdev_issue_zeroout as a non-invasive workaround. Signed-off-by: Christoph Hellwig <hch@lst.de> Reported-by: Junichi Nomura <j-nomura@ce.jp.nec.com> Fixes: e73c23ff ("block: add async variant of blkdev_issue_zeroout") Tested-by: Junichi Nomura <j-nomura@ce.jp.nec.com> Signed-off-by: Jens Axboe <axboe@fb.com>
Diffstat (limited to 'tools/virtio/ringtest/README')