[ { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", "BriefDescription": "DTLB load misses" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x80", "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "DTLB load miss large page walks" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x20", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", "BriefDescription": "DTLB load miss caused by low part of address" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", "BriefDescription": "DTLB second level hit" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "DTLB load miss page walks complete" }, { "EventCode": "0x8", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", "BriefDescription": "DTLB load miss page walk cycles" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", "BriefDescription": "DTLB misses" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x80", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "DTLB miss large page walks" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x20", "EventName": "DTLB_MISSES.PDE_MISS", "SampleAfterValue": "200000", "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE." }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", "BriefDescription": "DTLB first level misses but second level hit" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "DTLB miss page walks" }, { "EventCode": "0x49", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", "BriefDescription": "DTLB miss page walk cycles" }, { "EventCode": "0x4F", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", "BriefDescription": "Extended Page Table walk cycles" }, { "EventCode": "0xAE", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", "BriefDescription": "ITLB flushes" }, { "PEBS": "1", "EventCode": "0xC8", "Counter": "0,1,2,3", "UMask": "0x20", "EventName": "ITLB_MISS_RETIRED", "SampleAfterValue": "200000", "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", "BriefDescription": "ITLB miss" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x80", "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "ITLB miss large page walks" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", "BriefDescription": "ITLB miss page walks" }, { "EventCode": "0x85", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", "BriefDescription": "ITLB miss page walk cycles" }, { "PEBS": "1", "EventCode": "0xCB", "Counter": "0,1,2,3", "UMask": "0x80", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", "SampleAfterValue": "200000", "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" }, { "PEBS": "1", "EventCode": "0xC", "Counter": "0,1,2,3", "UMask": "0x1", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", "SampleAfterValue": "200000", "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" } ]> treef0a0f51d405c884e23f695695858d85f6260fec0 /drivers/usb/core/Makefile parent9579c4dc21292f375715d7acca439dac9855b3e9 (diff)
staging: greybus: timesync: validate platform state callback
When tearingdown timesync, and not in arche platform, the state platform callback is not initialized. That will trigger the following NULL dereferencing. CallTrace: ? gb_timesync_platform_unlock_bus+0x11/0x20 [greybus] gb_timesync_teardown+0x85/0xc0 [greybus] gb_timesync_svc_remove+0xab/0x190 [greybus] gb_svc_del+0x29/0x110 [greybus] gb_hd_del+0x14/0x20 [greybus] ap_disconnect+0x24/0x60 [gb_es2] usb_unbind_interface+0x7a/0x2c0 __device_release_driver+0x96/0x150 device_release_driver+0x1e/0x30 bus_remove_device+0xe7/0x130 device_del+0x116/0x230 usb_disable_device+0x97/0x1f0 usb_disconnect+0x80/0x260 hub_event+0x5ca/0x10e0 process_one_work+0x126/0x3b0 worker_thread+0x55/0x4c0 ? process_one_work+0x3b0/0x3b0 kthread+0xc4/0xe0 ? kthread_park+0xb0/0xb0 ret_from_fork+0x22/0x30 So, fix that by adding checks before use the callback. Fixes: 970dc85bd95d ("greybus: timesync: Add timesync core driver") Cc: <stable@vger.kernel.org> # 4.9.x Signed-off-by: Rui Miguel Silva <rmfrfs@gmail.com> Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Johan Hovold <johan@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/core/Makefile')