/* * POWER Data Stream Control Register (DSCR) SPR test * * This test modifies the DSCR value through both the SPR number * based mtspr instruction and then makes sure that the same is * reflected through mfspr instruction using either of the SPR * numbers. * * When using the privilege state SPR, the instructions such as * mfspr or mtspr are priviledged and the kernel emulates them * for us. Instructions using problem state SPR can be exuecuted * directly without any emulation if the HW supports them. Else * they also get emulated by the kernel. * * Copyright 2013, Anton Blanchard, IBM Corporation. * Copyright 2015, Anshuman Khandual, IBM Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published * by the Free Software Foundation. */ #include "dscr.h" static int check_dscr(char *str) { unsigned long cur_dscr, cur_dscr_usr; cur_dscr = get_dscr(); cur_dscr_usr = get_dscr_usr(); if (cur_dscr != cur_dscr_usr) { printf("%s set, kernel get %lx != user get %lx\n", str, cur_dscr, cur_dscr_usr); return 1; } return 0; } int dscr_user(void) { int i; check_dscr(""); for (i = 0; i < COUNT; i++) { set_dscr(i); if (check_dscr("kernel")) return 1; } for (i = 0; i < COUNT; i++) { set_dscr_usr(i); if (check_dscr("user")) return 1; } return 0; } int main(int argc, char *argv[]) { return test_harness(dscr_user, "dscr_user_test"); } ref='/cgit.cgi/linux/net-next.git/'>summaryrefslogtreecommitdiff
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authorBorislav Petkov <bp@suse.de>2017-01-20 21:29:40 +0100
committerThomas Gleixner <tglx@linutronix.de>2017-01-23 09:39:55 +0100
commitc26665ab5c49ad3e142e0f054ca3204f259ba09c (patch)
tree3bab11918e18e9d25ef7544dba05cdf39d1abec5 /sound/atmel
parent7a308bb3016f57e5be11a677d15b821536419d36 (diff)
x86/microcode/intel: Drop stashed AP patch pointer optimization
This was meant to save us the scanning of the microcode containter in the initrd since the first AP had already done that but it can also hurt us: Imagine a single hyperthreaded CPU (Intel(R) Atom(TM) CPU N270, for example) which updates the microcode on the BSP but since the microcode engine is shared between the two threads, the update on CPU1 doesn't happen because it has already happened on CPU0 and we don't find a newer microcode revision on CPU1. Which doesn't set the intel_ucode_patch pointer and at initrd jettisoning time we don't save the microcode patch for later application. Now, when we suspend to RAM, the loaded microcode gets cleared so we need to reload but there's no patch saved in the cache. Removing the optimization fixes this issue and all is fine and dandy. Fixes: 06b8534cb728 ("x86/microcode: Rework microcode loading") Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20170120202955.4091-2-bp@alien8.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'sound/atmel')