/* * Copyright (C) 2015 Anshuman Khandual, IBM Corporation. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ #define TAR_1 10 #define TAR_2 20 #define TAR_3 30 #define TAR_4 40 #define TAR_5 50 #define DSCR_1 100 #define DSCR_2 200 #define DSCR_3 300 #define DSCR_4 400 #define DSCR_5 500 #define PPR_1 0x4000000000000 /* or 31,31,31*/ #define PPR_2 0x8000000000000 /* or 1,1,1 */ #define PPR_3 0xc000000000000 /* or 6,6,6 */ #define PPR_4 0x10000000000000 /* or 2,2,2 */ char *user_read = "[User Read (Running)]"; char *user_write = "[User Write (Running)]"; char *ptrace_read_running = "[Ptrace Read (Running)]"; char *ptrace_write_running = "[Ptrace Write (Running)]"; char *ptrace_read_ckpt = "[Ptrace Read (Checkpointed)]"; char *ptrace_write_ckpt = "[Ptrace Write (Checkpointed)]"; int validate_tar_registers(unsigned long *reg, unsigned long tar, unsigned long ppr, unsigned long dscr) { int match = 1; if (reg[0] != tar) match = 0; if (reg[1] != ppr) match = 0; if (reg[2] != dscr) match = 0; if (!match) return TEST_FAIL; return TEST_PASS; } -back'>packet-rx-pump-back net-next plumbingsTobias Klauser
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authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /net/openvswitch/flow_table.h
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'net/openvswitch/flow_table.h')