/* Test context switching to see if the DSCR SPR is correctly preserved * when within a transaction. * * Note: We assume that the DSCR has been left at the default value (0) * for all CPUs. * * Method: * * Set a value into the DSCR. * * Start a transaction, and suspend it (*). * * Hard loop checking to see if the transaction has become doomed. * * Now that we *may* have been preempted, record the DSCR and TEXASR SPRS. * * If the abort was because of a context switch, check the DSCR value. * Otherwise, try again. * * (*) If the transaction is not suspended we can't see the problem because * the transaction abort handler will restore the DSCR to it's checkpointed * value before we regain control. */ #include #include #include #include #include #include "utils.h" #include "tm.h" #define SPRN_DSCR 0x03 int test_body(void) { uint64_t rv, dscr1 = 1, dscr2, texasr; SKIP_IF(!have_htm()); printf("Check DSCR TM context switch: "); fflush(stdout); for (;;) { rv = 1; asm __volatile__ ( /* set a known value into the DSCR */ "ld 3, %[dscr1];" "mtspr %[sprn_dscr], 3;" /* start and suspend a transaction */ "tbegin.;" "beq 1f;" "tsuspend.;" /* hard loop until the transaction becomes doomed */ "2: ;" "tcheck 0;" "bc 4, 0, 2b;" /* record DSCR and TEXASR */ "mfspr 3, %[sprn_dscr];" "std 3, %[dscr2];" "mfspr 3, %[sprn_texasr];" "std 3, %[texasr];" "tresume.;" "tend.;" "li %[rv], 0;" "1: ;" : [rv]"=r"(rv), [dscr2]"=m"(dscr2), [texasr]"=m"(texasr) : [dscr1]"m"(dscr1) , [sprn_dscr]"i"(SPRN_DSCR), [sprn_texasr]"i"(SPRN_TEXASR) : "memory", "r3" ); assert(rv); /* make sure the transaction aborted */ if ((texasr >> 56) != TM_CAUSE_RESCHED) { putchar('.'); fflush(stdout); continue; } if (dscr2 != dscr1) { printf(" FAIL\n"); return 1; } else { printf(" OK\n"); return 0; } } } int main(void) { return test_harness(test_body, "tm_resched_dscr"); } -next.git/diff/net/caif/chnl_net.c?h=nds-private-remove&id=4e5dbbda4c40a239e2ed4bbc98f2aa320e4dcca2'>diff
path: root/net/caif/chnl_net.c
0b9b6172d77e98eb72b94'>clps711x-clock.h
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authorGiovanni Cabiddu <giovanni.cabiddu@intel.com>2016-12-22 15:00:12 +0000
committerHerbert Xu <herbert@gondor.apana.org.au>2017-02-02 21:54:52 +0800
commit3484ecbe0e9deb94afb0b9b6172d77e98eb72b94 (patch)
tree4d4be0d20d4946c51ef47a882d78c9934a219c0e /include/dt-bindings/clock/clps711x-clock.h
parent11e3b725cfc282efe9d4a354153e99d86a16af08 (diff)
crypto: qat - fix bar discovery for c62x
Some accelerators of the c62x series have only two bars. This patch skips BAR0 if the accelerator does not have it. Cc: <stable@vger.kernel.org> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'include/dt-bindings/clock/clps711x-clock.h')