/* Test context switching to see if the DSCR SPR is correctly preserved * when within a transaction. * * Note: We assume that the DSCR has been left at the default value (0) * for all CPUs. * * Method: * * Set a value into the DSCR. * * Start a transaction, and suspend it (*). * * Hard loop checking to see if the transaction has become doomed. * * Now that we *may* have been preempted, record the DSCR and TEXASR SPRS. * * If the abort was because of a context switch, check the DSCR value. * Otherwise, try again. * * (*) If the transaction is not suspended we can't see the problem because * the transaction abort handler will restore the DSCR to it's checkpointed * value before we regain control. */ #include #include #include #include #include #include "utils.h" #include "tm.h" #define SPRN_DSCR 0x03 int test_body(void) { uint64_t rv, dscr1 = 1, dscr2, texasr; SKIP_IF(!have_htm()); printf("Check DSCR TM context switch: "); fflush(stdout); for (;;) { rv = 1; asm __volatile__ ( /* set a known value into the DSCR */ "ld 3, %[dscr1];" "mtspr %[sprn_dscr], 3;" /* start and suspend a transaction */ "tbegin.;" "beq 1f;" "tsuspend.;" /* hard loop until the transaction becomes doomed */ "2: ;" "tcheck 0;" "bc 4, 0, 2b;" /* record DSCR and TEXASR */ "mfspr 3, %[sprn_dscr];" "std 3, %[dscr2];" "mfspr 3, %[sprn_texasr];" "std 3, %[texasr];" "tresume.;" "tend.;" "li %[rv], 0;" "1: ;" : [rv]"=r"(rv), [dscr2]"=m"(dscr2), [texasr]"=m"(texasr) : [dscr1]"m"(dscr1) , [sprn_dscr]"i"(SPRN_DSCR), [sprn_texasr]"i"(SPRN_TEXASR) : "memory", "r3" ); assert(rv); /* make sure the transaction aborted */ if ((texasr >> 56) != TM_CAUSE_RESCHED) { putchar('.'); fflush(stdout); continue; } if (dscr2 != dscr1) { printf(" FAIL\n"); return 1; } else { printf(" OK\n"); return 0; } } } int main(void) { return test_harness(test_body, "tm_resched_dscr"); } b7a37184dd3d2172394e23d585d6'>commitdiff
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authorAndrei Vagin <avagin@openvz.org>2017-01-04 19:28:14 -0800
committerEric W. Biederman <ebiederm@xmission.com>2017-01-10 13:34:56 +1300
commitadd7c65ca426b7a37184dd3d2172394e23d585d6 (patch)
tree28b08b519540041b06ed0ab0b1c005076b932e8e /net/9p/trans_common.c
parent75422726b0f717d67db3283c2eb5bc14fa2619c5 (diff)
pid: fix lockdep deadlock warning due to ucount_lock
========================================================= [ INFO: possible irq lock inversion dependency detected ] 4.10.0-rc2-00024-g4aecec9-dirty #118 Tainted: G W --------------------------------------------------------- swapper/1/0 just changed the state of lock: (&(&sighand->siglock)->rlock){-.....}, at: [<ffffffffbd0a1bc6>] __lock_task_sighand+0xb6/0x2c0 but this lock took another, HARDIRQ-unsafe lock in the past: (ucounts_lock){+.+...} and interrupts could create inverse lock ordering between them. other info that might help us debug this: Chain exists of: &(&sighand->siglock)->rlock --> &(&tty->ctrl_lock)->rlock --> ucounts_lock Possible interrupt unsafe locking scenario: CPU0 CPU1 ---- ---- lock(ucounts_lock); local_irq_disable(); lock(&(&sighand->siglock)->rlock); lock(&(&tty->ctrl_lock)->rlock); <Interrupt> lock(&(&sighand->siglock)->rlock); *** DEADLOCK *** This patch removes a dependency between rlock and ucount_lock. Fixes: f333c700c610 ("pidns: Add a limit on the number of pid namespaces") Cc: stable@vger.kernel.org Signed-off-by: Andrei Vagin <avagin@openvz.org> Acked-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
Diffstat (limited to 'net/9p/trans_common.c')