/* * Copyright 2016, Cyril Bur, IBM Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. * * * Test the kernel's signal frame code. * * The kernel sets up two sets of ucontexts if the signal was to be * delivered while the thread was in a transaction. * Expected behaviour is that the checkpointed state is in the user * context passed to the signal handler. The speculated state can be * accessed with the uc_link pointer. * * The rationale for this is that if TM unaware code (which linked * against TM libs) installs a signal handler it will not know of the * speculative nature of the 'live' registers and may infer the wrong * thing. */ #include #include #include #include #include #include "utils.h" #include "tm.h" #define MAX_ATTEMPT 500000 #define NV_GPR_REGS 18 long tm_signal_self_context_load(pid_t pid, long *gprs, double *fps, vector int *vms, vector int *vss); static sig_atomic_t fail; static long gps[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, -1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,-16,-17,-18}; static void signal_usr1(int signum, siginfo_t *info, void *uc) { int i; ucontext_t *ucp = uc; ucontext_t *tm_ucp = ucp->uc_link; for (i = 0; i < NV_GPR_REGS && !fail; i++) { fail = (ucp->uc_mcontext.gp_regs[i + 14] != gps[i]); fail |= (tm_ucp->uc_mcontext.gp_regs[i + 14] != gps[i + NV_GPR_REGS]); if (fail) printf("Failed on %d GPR %lu or %lu\n", i, ucp->uc_mcontext.gp_regs[i + 14], tm_ucp->uc_mcontext.gp_regs[i + 14]); } } static int tm_signal_context_chk_gpr() { struct sigaction act; int i; long rc; pid_t pid = getpid(); SKIP_IF(!have_htm()); act.sa_sigaction = signal_usr1; sigemptyset(&act.sa_mask); act.sa_flags = SA_SIGINFO; if (sigaction(SIGUSR1, &act, NULL) < 0) { perror("sigaction sigusr1"); exit(1); } i = 0; while (i < MAX_ATTEMPT && !fail) { rc = tm_signal_self_context_load(pid, gps, NULL, NULL, NULL); FAIL_IF(rc != pid); i++; } return fail; } int main(void) { return test_harness(tm_signal_context_chk_gpr, "tm_signal_context_chk_gpr"); } ' value='nds-private-remove'/>
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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2017-01-29 15:07:34 +0300
committerDavid S. Miller <davem@davemloft.net>2017-01-30 22:05:43 -0500
commit1a0bee6c1e788218fd1d141db320db970aace7f0 (patch)
tree46c4116bc8ef4a7df718516a648597d9e21c15f1 /net/ipv4/devinet.c
parent63c190429020a9701b42887ac22c28f287f1762f (diff)
sh_eth: rename EESIPR bits
Since the commit b0ca2a21f769 ("sh_eth: Add support of SH7763 to sh_eth") the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with the *enum* declaring the EESR bits (interrupt status) WRT bit naming and formatting. I'd like to restore the consistency by using EESIPR as the bit name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the bits according to the available Renesas SH77{34|63} manuals; additionally, reconstruct couple names using the EESR bit declaration above... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'net/ipv4/devinet.c')