blob: 607bf01a31dd52ca09e6e379cf2b286b42b6a0a0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
|
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX1_H
#define __DT_BINDINGS_CLOCK_IMX1_H
#define IMX1_CLK_DUMMY 0
#define IMX1_CLK_CLK32 1
#define IMX1_CLK_CLK16M_EXT 2
#define IMX1_CLK_CLK16M 3
#define IMX1_CLK_CLK32_PREMULT 4
#define IMX1_CLK_PREM 5
#define IMX1_CLK_MPLL 6
#define IMX1_CLK_MPLL_GATE 7
#define IMX1_CLK_SPLL 8
#define IMX1_CLK_SPLL_GATE 9
#define IMX1_CLK_MCU 10
#define IMX1_CLK_FCLK 11
#define IMX1_CLK_HCLK 12
#define IMX1_CLK_CLK48M 13
#define IMX1_CLK_PER1 14
#define IMX1_CLK_PER2 15
#define IMX1_CLK_PER3 16
#define IMX1_CLK_CLKO 17
#define IMX1_CLK_UART3_GATE 18
#define IMX1_CLK_SSI2_GATE 19
#define IMX1_CLK_BROM_GATE 20
#define IMX1_CLK_DMA_GATE 21
#define IMX1_CLK_CSI_GATE 22
#define IMX1_CLK_MMA_GATE 23
#define IMX1_CLK_USBD_GATE 24
#define IMX1_CLK_MAX 25
#endif
|
