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path: root/include/dt-bindings/mfd/palmas.h
blob: cdb075aae4e1abdef5b26ae8b988850abed781ae (plain) 
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/*
 * This header provides macros for Palmas device bindings.
 *
 * Copyright (c) 2013, NVIDIA Corporation.
 *
 * Author: Laxman Dewangan <ldewangan@nvidia.com>
 *
 */

#ifndef __DT_BINDINGS_PALMAS_H
#define __DT_BINDINGS_PALMAS_H

/* External control pins */
#define PALMAS_EXT_CONTROL_PIN_ENABLE1	1
#define PALMAS_EXT_CONTROL_PIN_ENABLE2	2
#define PALMAS_EXT_CONTROL_PIN_NSLEEP	3

#endif /* __DT_BINDINGS_PALMAS_H */
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-10-18 12:24:51 +0000
egisters() on VLV/CHV. This will swap the order of DP AUX registration wrt. PPS initialization. There is an existing race here in case of a user space access via the DPAUX device node after DP AUX registration and before calling intel_dp_init_panel_power_sequencer_registers(), but this change won't make this worse. The fix for this is to separate DP AUX initialization and registration, that's a separate work already underway. The order of MST wrt. PPS init as well as the order of intel_dp_init_panel_power_sequencer_registers() wrt. intel_edp_panel_vdd_sanitize() also swap, which is ok, there are no dependencies between these steps. Suggested by Ville. CC: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1466499109-20240-4-git-send-email-imre.deak@intel.com
Diffstat
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c46
1 files changed, 24 insertions, 22 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c