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2015-02-16log: Add log_dbg() to facilitate debuggingTobias Klauser1-0/+5
2015-02-06Initial import, still work in progressTobias Klauser1-0/+28
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-10-05 10:03:37 +0000
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authorStefan Agner <stefan@agner.ch>2016-09-02 11:23:37 -0700
committerStefan Agner <stefan@agner.ch>2016-09-05 12:11:50 -0700
commit6cc4758ae91c0582f07e3c94c7de1ad0975feff5 (patch)
tree8de56d6849f1b971e908a4eefdd9276b835318ed
parent2b2fd56d7e92f134ecaae5c89e20f64dd0f95aa2 (diff)
drm/fsl-dcu: fix endian issue when using clk_register_divider
Since using clk_register_divider to setup the pixel clock, regmap is no longer used. Regmap did take care of DCU using different endianness. Check endianness using the device-tree property "big-endian" to determine the location of DIV_RATIO. Cc: stable@vger.kernel.org Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel clock divider") Reported-by: Meng Yi <meng.yi@nxp.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Meng Yi <meng.yi@nxp.com>
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