/* * Copyright (C) 2014-2015 Tobias Klauser * Copyright (C) 2009-2012 Daniel Borkmann * * This file is part of llmnrd. * * llmnrd is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * llmnrd is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with llmnrd. If not, see . */ #include #include #include "util.h" void *xmalloc(size_t size) { void *ptr; if (size == 0) panic("malloc: size 0\n"); ptr = malloc(size); if (!ptr) panic("malloc: out of memory\n"); return ptr; } void *xzalloc(size_t size) { void *ptr = xmalloc(size); memset(ptr, 0, size); return ptr; } void *xrealloc(void *ptr, size_t size) { void *newptr; if (size == 0) panic("realloc: size 0\n"); newptr = realloc(ptr, size); if (!newptr) { free(ptr); panic("realloc: out of memory\n"); } return newptr; } char *xstrdup(const char *s) { size_t len = strlen(s) + 1; char *ret = xmalloc(len); memcpy(ret, s, len); return ret; } ype='submit' value='switch'/> net-next plumbingsTobias Klauser
summaryrefslogtreecommitdiff
path: root/Documentation
diff options
context:
space:
mode:
authorLars-Peter Clausen <lars@metafoo.de>2016-02-04 17:13:30 +0100
committerMark Brown <broonie@kernel.org>2016-02-05 18:12:57 +0000
commitb1353d1c1d4555b7c40066fa2cacc7da266e9904 (patch)
tree9312609fe10097a2d44da7f5a813d75dc5c6017a /Documentation
parent2ec3b6287b12a7131c28cd9408b368cd451bdc48 (diff)
spi: Add Analog Devices AXI SPI Engine controller support
This patch adds support for the AXI SPI Engine controller which is a FPGA soft-peripheral which is used in some of Analog Devices' reference designs. The AXI SPI Engine controller is part of the SPI Engine framework[1] and allows memory mapped access to the SPI Engine control bus. This allows it to be used as a general purpose software driven SPI controller. The SPI Engine in addition offers some optional advanced acceleration and offloading capabilities, which are not part of this patch though and will be introduced separately. At the core of the SPI Engine framework is a small sort of co-processor that accepts a command stream and turns the commands into low-level SPI transactions. Communication is done through three memory mapped FIFOs in the register map of the AXI SPI Engine peripheral. One FIFO for the command stream and one each for transmit and receive data. The driver translates a spi_message in a command stream and writes it to the peripheral which executes it asynchronously. This allows it to perform very precise timings which are required for some SPI slave devices to achieve maximum performance (e.g. analog-to-digital and digital-to-analog converters). The execution flow is synchronized to the host system by a special synchronize instruction which generates a interrupt. [1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation')