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authorVadim Kochan <vadim4j@gmail.com>2016-08-13 02:11:14 +0300
committerTobias Klauser <tklauser@distanz.ch>2016-09-21 09:54:58 +0200
commit8eb426c88c983ae6f81d813b75e8ca9a9a0b07b5 (patch)
tree0abb142d066177c621ec1a9c7ea438776e78c256 /screen.h
parent573b1fff25af70492deb9e59c0b48d77b0c1ed03 (diff)
trafgen: icmpv4: Update csum at runtime if needed
Update csum if any of the ICMPv4 field was changed. Signed-off-by: Vadim Kochan <vadim4j@gmail.com> Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Diffstat (limited to 'screen.h')
0 files changed, 0 insertions, 0 deletions
='2' class='oid'>c40d8883a28ece32d753d96e77f05e5e9a7c4415 (diff)
Merge branch 'cpsw-cpdma-DDR'
Grygorii Strashko says: ==================== net: ethernet: ti: cpsw: support placing CPDMA descriptors into DDR This series intended to add support for placing CPDMA descriptors into DDR by introducing new module parameter "descs_pool_size" to specify size of descriptor's pool. The "descs_pool_size" defines total number of CPDMA CPPI descriptors to be used for both ingress/egress packets processing. If not specified - the default value 256 will be used which will allow to place descriptor's pool into the internal CPPI RAM. In addition, added ability to re-split CPDMA pool of descriptors between RX and TX path via ethtool '-G' command wich will allow to configure and fix number of descriptors used by RX and TX path, which, then, will be split between RX/TX channels proportionally depending on number of RX/TX channels and its weight. This allows significantly to reduce UDP packets drop rate for bandwidth >301 Mbits/sec (am57x). Before enabling this feature, the am437x SoC has to be fixed as it's proved that it's not working when CPDMA descriptors placed in DDR. So, the patch 1 fixes this issue. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation/kernel-per-CPU-kthreads.txt')