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| author | Vadim Kochan <vadim4j@gmail.com> | 2016-02-08 08:01:51 +0200 |
|---|---|---|
| committer | Tobias Klauser <tklauser@distanz.ch> | 2016-02-23 13:15:50 +0100 |
| commit | f02fcdbd2cb4dc041783def773e446c179bd57f1 (patch) | |
| tree | 9c1167852b94242eec1fa7aa4f03c6df31f0c04d /sysctl.c | |
| parent | b14fd7ed1bdbe0644601b9f0e854af1b19811f30 (diff) | |
trafgen: proto: Fix bad field masking
Current logic does OR of existing field value & shift-masked
specified value, which is not enough as 0s bits from
the specified value will be not set (be cause of OR),
so fixed it by reseting original field value by AND with
reverted field mask, in otherwords - bits part of original field
value is reset to 0s and only after OR-ed with specified shift-masked
value.
Signed-off-by: Vadim Kochan <vadim4j@gmail.com>
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Diffstat (limited to 'sysctl.c')
0 files changed, 0 insertions, 0 deletions