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authorTobias Klauser <tklauser@distanz.ch>2016-12-16 12:02:06 +0100
committerTobias Klauser <tklauser@distanz.ch>2016-12-16 12:02:06 +0100
commit374141decf7c9978fd2c535099440d68e11e7683 (patch)
treee4319060aea90473e47488a04f09ea995a609d59 /tprintf.c
parent074f8fc82ff26bb02c3c09f6ed71bca77e08e020 (diff)
trafgen: proto: Zero out the correct packet slot
In the third attempt, finally do the packet slot zeroing correctly. Zero the struct packet in __init_new_packet_slot() not the struct packet_dyn in __init_new_counter_slot(). Don't know what hit me yesterday... Fixes: d6d511ecff24 ("trafgen: proto: Zero out newly allocated struct packet") Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Diffstat (limited to 'tprintf.c')
0 files changed, 0 insertions, 0 deletions
s converted into the GAS BitWidth field, its Address is converted into the GAS Address field, and the GAS AccessSize field is left 0 but most of the registers actually cannot be accessed using "ANY" accesses. As a conclusion, when AccessSize = 0 (ANY), the Address should either be aligned to the BitWidth (wrong conversion) or aligned to 32 for PIO or 64 for MMIO (real GAS). Since currently, max_bit_width is 32, then: 1. BitWidth for the wrong conversion is 8,16,32; and 2. The Address of the real GAS should always be aligned to 8,16,32. The address alignment check to exclude false matched real GAS is not necessary. Thus this patch fixes the issue by removing the address alignment check. On the other hand, we in fact could use a simpler check of "reg->bit_width < max_bit_width" to exclude the "BitWidth=64 PIO" case that may be issued from acpi_read()/acpi_write() in the future. Fixes: b314a172ee96 (ACPICA: Hardware: Add optimized access bit width support) Reported-and-tested-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Acked-by: Mike Marshall <hubcap@omnibond.com> Suggested-by: Jan Beulich <jbeulich@suse.com> Signed-off-by: Lv Zheng <lv.zheng@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'Documentation')