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0 files changed, 0 insertions, 0 deletions
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-10-05 17:39:18 +0000
authorMika Kahola <mika.kahola@intel.com>2016-09-09 14:10:55 +0300
committerJani Nikula <jani.nikula@intel.com>2016-09-15 14:50:55 +0300
commit70ec064516cc45525f7072f9e57ff780e987f0cd (patch)
treef1adb270612443c559842130f695135c1e3bcfb5 /drivers/gpu/drm/i915/intel_dp.c
parent1a2724fa94b6308dee87f7851be7ec84a409a538 (diff)
drm/i915: Check pixel rate for DP to VGA dongle
Filter out a mode that exceeds the max pixel rate setting for DP to VGA dongle. This is defined in DPCD register 0x81 if detailed cap info i.e. info field is 4 bytes long and it is available for DP downstream port. The register defines the pixel rate divided by 8 in MP/s. v2: DPCD read outs and computation moved to drm (Ville, Daniel) v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock() function (Daniel) v4: Use of drm_dp_helper.c routines to compute max pixel clock (Ville) v5: Use of intel_dp->downstream_ports to read out port capabilities. Code restructuring (Ville) v6: Move DP branch device check to drm_dp_helper.c (Daniel) v7: Cleanup as suggested by Ville Reviewed-by: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1473419458-17080-10-git-send-email-mika.kahola@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c27
1 files changed, 26 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c