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CLK divider when setting up master clocks
If the McASP is used as clock master and the reference clock is AUXCLK we can have additional level of divider. The BCLK divider is limited to maximum 32, if the desired bclk can not be reached with this, the AUXCLK divider also needs to be used. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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