cxgb4: Set VPD size so we can read both VPD structures

Chelsio adapters have two VPD structures stored in the VPD:

  - offset 0x000: an abbreviated VPD, and
  - offset 0x400: the complete VPD.

After 104daa71b396 ("PCI: Determine actual VPD size on first access"), the
PCI core computes the valid VPD size by parsing the VPD starting at offset
0x0.  That size only includes the abbreviated VPD structure, so reads of
the complete VPD at 0x400 fail.

Explicitly set the VPD size with pci_set_vpd_size() so the driver can read
both VPD structures.

[bhelgaas: changelog, split patches, rename to pci_set_vpd_size() and
return int (not ssize_t)]
Fixes: 104daa71b396 ("PCI: Determine actual VPD size on first access")
Tested-by: Steve Wise <swise@opengridcomputing.com>
Signed-off-by: Casey Leedom <leedom@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/flowtop/Makefile b/flowtop/Makefile
index cb57cb3..bc7afb5 100644
--- a/flowtop/Makefile
+++ b/flowtop/Makefile
@@ -30,7 +30,8 @@ flowtop-objs +=	geoip.o \
 		ioops.o
 endif
 
-flowtop-eflags = $(shell $(PKG_CONFIG) --cflags ncurses)
+flowtop-eflags = $(shell $(PKG_CONFIG) --cflags ncurses) \
+                 $(shell $(PKG_CONFIG) --cflags libnetfilter_conntrack)
 
 flowtop-confs =	tcp.conf \
 		udp.conf \