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generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-09-18 20:18:17 +0000
he sor_src clock via a second mux. Previous generations of Tegra have only supported eDP and LVDS with the SOR, where LVDS was never used on publicly available hardware. Clocking for this only ever required the first level mux (to select between sor_safe and sor_brick). Tegra210 has a new revision of the SOR that supports HDMI and hence needs to support the second level mux to allow selecting pll_d2_out0 as the SOR clock's parent. This second mux is knows as sor_src, and operating system software needs a reference to it in order to select the proper parent. Signed-off-by: Thierry Reding <treding@nvidia.com>
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