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2013-03-15docs: add initial workflow documentDaniel Borkmann1-0/+64
Trying to document the workflow that comes along with using this Git repository. Further ideas, additions to this document are welcome to create a unified frame for all maintainers, developers and (advanced) users. Signed-off-by: Daniel Borkmann <dborkman@redhat.com>
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-09-19 23:02:54 +0000
0475aed3731ee32'>2bc0ff0b5e4711eda336dacc75098b2886c8fa8b parentae4df11a0f538b83781cf120a78dde32b0070600 (diff)
drm/exynos: use logical AND in exynos_drm_plane_check_size()
The current bitwise AND should result in the same assembler but this is what the code is actually supposed to do. Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1464179407-9004-1-git-send-email-tjakobi@math.uni-bielefeld.de
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