summaryrefslogtreecommitdiff
path: root/bpf_ext.h
AgeCommit message (Expand)AuthorFilesLines
2013-06-04bpf: split up instructions and extensions from headerDaniel Borkmann1-0/+47
dt' onchange='this.form.submit();'>
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2016-08-02 12:39:43 +1000
committerMichael Ellerman <mpe@ellerman.id.au>2016-08-09 14:50:18 +1000
commit880a3d6afd068682d6386a0528be1217541d3d8e (patch)
treededfb680126a31a23e92cebae47a3a41ad6aef40
parentd2cf5be07ff7c7cde8bef8551a30e8e86e2037a7 (diff)
powerpc/xics: Properly set Edge/Level type and enable resend
This sets the type of the interrupt appropriately. We set it as follow: - If not mapped from the device-tree, we use edge. This is the case of the virtual interrupts and PCI MSIs for example. - If mapped from the device-tree and #interrupt-cells is 2 (PAPR compliant), we use the second cell to set the appropriate type - If mapped from the device-tree and #interrupt-cells is 1 (current OPAL on P8 does that), we assume level sensitive since those are typically going to be the PSI LSIs which are level sensitive. Additionally, we mark the interrupts requested via the opal_interrupts property all level. This is a bit fishy but the best we can do until we fix OPAL to properly expose them with a complete descriptor. It is also correct for the current HW anyway as OPAL interrupts are currently PCI error and PSI interrupts which are level. Finally now that edge interrupts are properly identified, we can enable CONFIG_HARDIRQS_SW_RESEND which will make the core re-send them if they occur while masked, which some drivers rely upon. This fixes issues with lost interrupts on some Mellanox adapters. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat