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path: root/trafgen_l2.h
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2016-10-04trafgen: l2: Add support for PFC headerVadim Kochan1-0/+21
2016-10-04trafgen: l2: Add support for IEEE 802.3X PAUSE headerVadim Kochan1-0/+5
2016-02-23trafgen: l2: Add MPLS header generationVadim Kochan1-0/+7
2016-02-02trafgen: l2: Add VLAN header generationVadim Kochan1-0/+9
2016-01-29trafgen: parser: Support "etype"/"type" keywords for EthertypeTobias Klauser1-1/+1
2016-01-28trafgen: l2: Add ARP header generation logicVadim Kochan1-0/+12
2016-01-28trafgen: l2: Add Ethernet protocol header generationVadim Kochan1-0/+12
also need to be accessed for some SoCs. The QSPI_SPI_SETUP_REGx needs to be populated with flash specific information like read opcode, read mode(quad, dual, normal), address width and dummy bytes. Once, controller is in mmap mode, the whole flash memory is available as a memory region at SoC specific address. This region can be accessed using normal memcpy() (or mem-to-mem dma copy). The ti-qspi controller hardware will internally communicate with SPI flash over SPI bus and get the requested data. Implement spi_flash_read() callback to support mmap read over SPI flash devices. With this, the read throughput increases from ~100kB/s to ~2.5 MB/s. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation/devicetree')