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| author | Gabriele Paoloni <gabriele.paoloni@huawei.com> | 2016-04-16 12:03:39 +0100 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-05-02 16:11:48 -0500 |
| commit | a5cb903aef8c642e6f0f6810d46dacedf666b54a (patch) | |
| tree | 8916cb64f4260283d7bc9cfeefc3a254b7a113ca /Documentation/devicetree | |
| parent | 7e57fd1444bf8f4ba9179f826ed6817c56b801d4 (diff) | |
PCI: designware: Remove incorrect RC memory base/limit configuration
Currently dw_pcie_setup_rc() configures memory base and memory limit in the
type1 configuration header for the root complex. In doing so it uses the
CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr).
This is wrong and it is useless since the configuration is overwritten
later on when pci_bus_assign_resources() is called.
Remove this configuration from dw_pcie_setup_rc().
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
Diffstat (limited to 'Documentation/devicetree')