From f26175af848bfb3faaedd98b402949e8bd7ab8bc Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Mon, 1 Feb 2016 15:56:10 +0100 Subject: trafgen: parser: Add TCP header generation function Add a function 'tcp()' to generate TCP headers from the trafgen configuration language. Fields supported: sp|sport TCP source port (default 0) dp|dport TCP destination port (default 0) seq Sequence number (default: 0) aseq|ackseq Acknowledgement number (default 0) doff|hlen Header length/data offset (default: 5) cwr Congestion Window Reduced flag (default: 0) ece|ecn ECN-Echo flag (default: 0) urg Urgent flag (default: 0) ack Acknowledgement flag (default: 0) psh Push flag (default: 0) rst Reset flag (default: 0) syn Synchronize flag (default: 0) fin Finish flag (default: 0) win|window Receive window size (default: 0) csum Checksum field (calculated automatically) urgptr Urgent pointer (default: 0) Example (SYN on port 80/http): { tcp(dport=80, syn, window=5840) } Signed-off-by: Tobias Klauser --- trafgen_l4.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'trafgen_l4.c') diff --git a/trafgen_l4.c b/trafgen_l4.c index 286e54a..7f80e74 100644 --- a/trafgen_l4.c +++ b/trafgen_l4.c @@ -21,6 +21,26 @@ static struct proto_field udp_fields[] = { { .id = UDP_CSUM, .len = 2, .offset = 6 }, }; +static struct proto_field tcp_fields[] = { + { .id = TCP_SPORT, .len = 2, .offset = 0 }, + { .id = TCP_DPORT, .len = 2, .offset = 2 }, + { .id = TCP_SEQ, .len = 4, .offset = 4 }, + { .id = TCP_ACK_SEQ, .len = 4, .offset = 8 }, + { .id = TCP_DOFF, .len = 2, .offset = 12, .shift = 12, .mask = 0xf000 }, + /* reserved (4 bits) */ + { .id = TCP_CWR, .len = 2, .offset = 12, .shift = 7, .mask = 0x0080 }, + { .id = TCP_ECE, .len = 2, .offset = 12, .shift = 6, .mask = 0x0040 }, + { .id = TCP_URG, .len = 2, .offset = 12, .shift = 5, .mask = 0x0020 }, + { .id = TCP_ACK, .len = 2, .offset = 12, .shift = 4, .mask = 0x0010 }, + { .id = TCP_PSH, .len = 2, .offset = 12, .shift = 3, .mask = 0x0008 }, + { .id = TCP_RST, .len = 2, .offset = 12, .shift = 2, .mask = 0x0004 }, + { .id = TCP_SYN, .len = 2, .offset = 12, .shift = 1, .mask = 0x0002 }, + { .id = TCP_FIN, .len = 2, .offset = 12, .shift = 0, .mask = 0x0001 }, + { .id = TCP_WINDOW, .len = 2, .offset = 14 }, + { .id = TCP_CSUM, .len = 2, .offset = 16 }, + { .id = TCP_URG_PTR, .len = 2, .offset = 18 }, +}; + static void udp_header_init(struct proto_hdr *hdr) { struct proto_hdr *lower; @@ -65,7 +85,51 @@ static struct proto_hdr udp_hdr = { .packet_finish = udp_packet_finish, }; +static void tcp_header_init(struct proto_hdr *hdr) +{ + struct proto_hdr *lower; + + proto_lower_default_add(PROTO_IP4); + + lower = proto_current_header(); + + if (lower->id == PROTO_IP4) + proto_field_set_default_u8(lower, IP4_PROTO, IPPROTO_TCP); + + proto_header_fields_add(hdr, tcp_fields, array_size(tcp_fields)); + + proto_field_set_default_be16(hdr, TCP_DOFF, 5); +} + +static void tcp_packet_finish(struct proto_hdr *hdr) +{ + struct proto_hdr *lower = proto_lower_header(hdr); + struct packet *pkt = current_packet(); + uint16_t total_len; + uint16_t csum; + + if (proto_field_is_set(hdr, TCP_CSUM)) + return; + + if (!lower || lower->id != PROTO_IP4) + return; + + total_len = pkt->len - hdr->pkt_offset; + csum = p4_csum((void *) proto_header_ptr(lower), proto_header_ptr(hdr), + total_len, IPPROTO_TCP); + + proto_field_set_be16(hdr, TCP_CSUM, bswap_16(csum)); +} + +static struct proto_hdr tcp_hdr = { + .id = PROTO_TCP, + .layer = PROTO_L4, + .header_init = tcp_header_init, + .packet_finish = tcp_packet_finish, +}; + void protos_l4_init(void) { proto_header_register(&udp_hdr); + proto_header_register(&tcp_hdr); } -- cgit v1.2.3-54-g00ecf value='8'>8space:mode:
authorBjorn Helgaas <bhelgaas@google.com>2016-09-01 08:52:29 -0500
committerBjorn Helgaas <bhelgaas@google.com>2016-09-01 08:52:29 -0500
commit6af7e4f77259ee946103387372cb159f2e99a6d4 (patch)
treebd17c2d31bbb2bbabfb85a564bcb8ed9807d7ba6 /Documentation/kobject.txt
parent21c80c9fefc3db10b530a96eb0478c29eb28bf77 (diff)
PCI: Mark Haswell Power Control Unit as having non-compliant BARs
The Haswell Power Control Unit has a non-PCI register (CONFIG_TDP_NOMINAL) where BAR 0 is supposed to be. This is erratum HSE43 in the spec update referenced below: The PCIe* Base Specification indicates that Configuration Space Headers have a base address register at offset 0x10. Due to this erratum, the Power Control Unit's CONFIG_TDP_NOMINAL CSR (Bus 1; Device 30; Function 3; Offset 0x10) is located where a base register is expected. Mark the PCU as having non-compliant BARs so we don't try to probe any of them. There are no other BARs on this device. Rename the quirk so it's not Broadwell-specific. Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-datasheet-vol-2.html (section 5.4, Device 30 Function 3) Link: https://bugzilla.kernel.org/show_bug.cgi?id=153881 Reported-by: Paul Menzel <pmenzel@molgen.mpg.de> Tested-by: Prarit Bhargava <prarit@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Myron Stowe <myron.stowe@redhat.com>
Diffstat (limited to 'Documentation/kobject.txt')