/* * Subject to the GPL, version 2. */ #include "xmalloc.h" struct panic_handler { void *arg; pid_t pid; bool is_enabled; void (*on_panic)(void *arg); struct panic_handler *next; }; static struct panic_handler *panic_handlers; void panic_handler_add(void (*on_panic)(void *arg), void *arg) { struct panic_handler *handler = xmallocz(sizeof(*handler)); handler->arg = arg; handler->pid = getpid(); handler->is_enabled = true; handler->on_panic = on_panic; handler->next = panic_handlers; panic_handlers = handler; }; void call_panic_handlers(void) { struct panic_handler *it; pid_t pid = getpid(); for (it = panic_handlers; it; it = it->next) { if (it->pid == pid && it->is_enabled) { it->is_enabled = false; it->on_panic(it->arg); } } } index : net-next.git
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authorGeert Uytterhoeven <geert+renesas@glider.be>2016-01-11 19:41:12 +0100
committerSimon Horman <horms+renesas@verge.net.au>2016-04-20 08:52:55 +1000
commitc531fb27e9699eaee478ee5686a3cca5dee73602 (patch)
treeff4a270a520ba262221fa5b0ff7b67d45d8548c2
parent01638a7f5ef967e94e8aff455874d62e12fe32ed (diff)
ARM: shmobile: timer: Fix preset_lpj leading to too short delays
On all shmobile ARM SoCs, loop-based delays may complete early, which can be after only 1/3 (Cortex A9) or 1/2 (Cortex A7 or A15) of the minimum required time. This is caused by calculating preset_lpj based on incorrect assumptions about the number of clock cycles per loop: - All of Cortex A7, A9, and A15 run __loop_delay() at 1 loop per CPU clock cycle, - As of commit 11d4bb1bd067f9d0 ("ARM: 7907/1: lib: delay-loop: Add align directive to fix BogoMIPS calculation"), Cortex A8 runs __loop_delay() at 1 loop per 2 instead of 3 CPU clock cycles. On SoCs with Cortex A7 and/or A15 CPU cores, this went unnoticed, as delays use the ARM arch timer if available. R-Car Gen2 doesn't work if the arch timer is disabled. However, APE6 can be used without the arch timer. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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