#include #include #include "epoll2.h" #include "die.h" void set_epoll_descriptor(int fd_epoll, int action, int fd_toadd, int events) { int ret; struct epoll_event ev; memset(&ev, 0, sizeof(ev)); ev.events = events; ev.data.fd = fd_toadd; ret = epoll_ctl(fd_epoll, action, fd_toadd, &ev); if (ret < 0) panic("Cannot add socket for epoll!\n"); } int set_epoll_descriptor2(int fd_epoll, int action, int fd_toadd, int events) { struct epoll_event ev; memset(&ev, 0, sizeof(ev)); ev.events = events; ev.data.fd = fd_toadd; return epoll_ctl(fd_epoll, action, fd_toadd, &ev); } Git repository'/>
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authorLukasz Majewski <lukma@denx.de>2017-02-07 06:20:24 +0100
committerDavid S. Miller <davem@davemloft.net>2017-02-07 13:59:27 -0500
commitac6e058b75be71208e98a5808453aae9a17be480 (patch)
tree559b0039d832be0016c2f200e4376299ef7a5ced /drivers
parentfc6d39c39581f3c12c95f166ce95ef8beb2047e8 (diff)
net: phy: dp83867: Recover from "port mirroring" N/A MODE4
The DP83867 when not properly bootstrapped - especially with LED_0 pin - can enter N/A MODE4 for "port mirroring" feature. To provide normal operation of the PHY, one needs not only to explicitly disable the port mirroring feature, but as well stop some IC internal testing (which disables RGMII communication). To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit 11 examined. When it is set, the another RESERVED bit (11) at PHYCR (0x0010) register must be clear to disable testing mode and enable RGMII communication. Thorough explanation of the problem can be found at following e2e thread: "DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) - Linux driver" https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954 Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')