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| author | Atish Patra <atish.patra@oracle.com> | 2016-10-19 18:33:29 -0600 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2016-10-24 11:04:17 -0700 |
| commit | d624716b6c67e60681180786564b92ddb521148a (patch) | |
| tree | 515fe225d781a617412e64dfa36aa1056cf9bd25 /Documentation/devicetree/bindings/net/marvell-neta-bm.txt | |
| parent | 07d9a380680d1c0eb51ef87ff2eab5c994949e69 (diff) | |
sparc64: Setup a scheduling domain for highest level cache.
Individual scheduler domain should consist different hierarchy
consisting of cores sharing similar property. Currently, no
scheduler domain is defined separately for the cores that shares
the last level cache. As a result, the scheduler fails to take
advantage of cache locality while migrating tasks during load
balancing.
Here are the cpu masks currently present for sparc that are/can
be used in scheduler domain construction.
cpu_core_map : set based on the cores that shares l1 cache.
core_core_sib_map : is set based on the socket id.
The prior SPARC notion of socket was defined as highest level of
shared cache. However, the MD record on T7 platforms now describes
the CPUs that share the physical socket and this is no longer tied
to shared cache.
That's why a separate cpu mask needs to be created that truly
represent highest level of shared cache for all platforms.
Signed-off-by: Atish Patra <atish.patra@oracle.com>
Reviewed-by: Chris Hyser <chris.hyser@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation/devicetree/bindings/net/marvell-neta-bm.txt')