#ifndef LIST_I_H #define LIST_I_H #include #include #define list_head cds_list_head #define LIST_HEAD CDS_LIST_HEAD #define INIT_LIST_HEAD CDS_INIT_LIST_HEAD #define LIST_HEAD_INIT CDS_LIST_HEAD_INIT #define list_add cds_list_add #define list_add_tail cds_list_add_tail #define list_del cds_list_del #define list_del_init cds_list_del_init #define list_move cds_list_move #define list_replace cds_list_replace #define list_splice cds_list_splice #define list_entry cds_list_entry #define list_first_entry cds_list_first_entry #define list_for_each cds_list_for_each #define list_for_each_safe cds_list_for_each_safe #define list_for_each_prev cds_list_for_each_prev #define list_for_each_prev_safe cds_list_for_each_prev_safe #define list_for_each_entry cds_list_for_each_entry #define list_for_each_entry_safe cds_list_for_each_entry_safe #define list_for_each_entry_reverse cds_list_for_each_entry_reverse #define list_empty cds_list_empty #define list_replace_init cds_list_replace_init #define list_add_rcu cds_list_add_rcu #define list_add_tail_rcu cds_list_add_tail_rcu #define list_replace_rcu cds_list_replace_rcu #define list_del_rcu cds_list_del_rcu #define list_for_each_rcu cds_list_for_each_rcu #define list_for_each_entry_rcu cds_list_for_each_entry_rcu #endif /* LIST_I_H */ ack'>packet-rx-pump-back net-next plumbingsTobias Klauser
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authorAtish Patra <atish.patra@oracle.com>2016-10-19 18:33:29 -0600
committerDavid S. Miller <davem@davemloft.net>2016-10-24 11:04:17 -0700
commitd624716b6c67e60681180786564b92ddb521148a (patch)
tree515fe225d781a617412e64dfa36aa1056cf9bd25 /Documentation/i2c
parent07d9a380680d1c0eb51ef87ff2eab5c994949e69 (diff)
sparc64: Setup a scheduling domain for highest level cache.
Individual scheduler domain should consist different hierarchy consisting of cores sharing similar property. Currently, no scheduler domain is defined separately for the cores that shares the last level cache. As a result, the scheduler fails to take advantage of cache locality while migrating tasks during load balancing. Here are the cpu masks currently present for sparc that are/can be used in scheduler domain construction. cpu_core_map : set based on the cores that shares l1 cache. core_core_sib_map : is set based on the socket id. The prior SPARC notion of socket was defined as highest level of shared cache. However, the MD record on T7 platforms now describes the CPUs that share the physical socket and this is no longer tied to shared cache. That's why a separate cpu mask needs to be created that truly represent highest level of shared cache for all platforms. Signed-off-by: Atish Patra <atish.patra@oracle.com> Reviewed-by: Chris Hyser <chris.hyser@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation/i2c')