/* * netsniff-ng - the packet sniffing beast * Copyright 2012 Markus Amend , Deutsche Flugsicherung GmbH * Subject to the GPL, version 2. * * IPv6 Fragmentation Header described in RFC2460 */ #include #include #include /* for ntohs() */ #include "proto.h" #include "dissector_eth.h" #include "built_in.h" #include "pkt_buff.h" struct fragmhdr { uint8_t h_fragm_next_header; uint8_t h_fragm_reserved; uint16_t h_fragm_off_res_M; uint32_t h_fragm_identification; } __packed; static void fragm(struct pkt_buff *pkt) { uint16_t off_res_M; struct fragmhdr *fragm_ops; fragm_ops = (struct fragmhdr *) pkt_pull(pkt, sizeof(*fragm_ops)); if (fragm_ops == NULL) return; off_res_M = ntohs(fragm_ops->h_fragm_off_res_M); tprintf("\t [ Fragment "); tprintf("NextHdr (%u), ", fragm_ops->h_fragm_next_header); tprintf("Reserved (%u), ", fragm_ops->h_fragm_reserved); tprintf("Offset (%u), ", off_res_M >> 3); tprintf("Res (%u), ", (off_res_M >> 1) & 0x3); tprintf("M flag (%u), ", off_res_M & 0x1); tprintf("Identification (%u)", ntohl(fragm_ops->h_fragm_identification)); tprintf(" ]\n"); pkt_set_proto(pkt, ð_lay3, fragm_ops->h_fragm_next_header); } static void fragm_less(struct pkt_buff *pkt) { uint16_t off_res_M; struct fragmhdr *fragm_ops; fragm_ops = (struct fragmhdr *) pkt_pull(pkt, sizeof(*fragm_ops)); if (fragm_ops == NULL) return; off_res_M = ntohs(fragm_ops->h_fragm_off_res_M); tprintf(" FragmOffs %u", off_res_M >> 3); pkt_set_proto(pkt, ð_lay3, fragm_ops->h_fragm_next_header); } struct protocol ipv6_fragm_ops = { .key = 0x2C, .print_full = fragm, .print_less = fragm_less, }; ef='/cgit.cgi/linux/net-next.git/log/?h=nds-private-remove'>logtreecommitdiff
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authorJoel Stanley <joel@jms.id.au>2016-09-22 08:35:00 +0930
committerDavid S. Miller <davem@davemloft.net>2016-09-22 03:31:14 -0400
commit2a0ab8ebbec634127987fc8dbbd09a7fd7274e3d (patch)
tree5fff6131219a7d63df7bfa9d13b44bf75442d5f2
parent7906a4da0ef845d01e76f2187c23cc71ae00fa1d (diff)
net/faraday: Adapt for Aspeed SoCs
The RXDES and TXDES registers bits in the ftgmac100 indicates EDO{R,T}R at bit position 15 for the Faraday Tech IP. However, the version of this IP present in the Aspeed SoCs has these bits at position 30 in the registers. It appers that ast2400 SoCs support both positions, with the 15th bit marked as reserved but still functional. In the ast2500 this bit is reused for another function, so we need a work around. This was confirmed with engineers from Aspeed that using bit 30 is correct for both the ast2400 and ast2500 SoCs. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: David S. Miller <davem@davemloft.net>