#include #include #include "sig.h" void register_signal(int signal, void (*handler)(int)) { sigset_t block_mask; struct sigaction saction; sigfillset(&block_mask); saction.sa_handler = handler; saction.sa_mask = block_mask; saction.sa_flags = SA_RESTART; sigaction(signal, &saction, NULL); } void register_signal_f(int signal, void (*handler)(int), int flags) { sigset_t block_mask; struct sigaction saction; sigfillset(&block_mask); saction.sa_handler = handler; saction.sa_mask = block_mask; saction.sa_flags = flags; sigaction(signal, &saction, NULL); } tle='net-next.git Git repository'/>
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authorThierry Reding <treding@nvidia.com>2016-06-23 12:04:24 +0200
committerThierry Reding <treding@nvidia.com>2016-07-14 14:57:00 +0200
commit5d2304c1de6b353a0e09f4ed22165835f5651e4b (patch)
treeaa707bb1b9e1e18905b8b527274addd092e9747e /Documentation/devicetree
parentb299221ca99683e50ea03ac8ca638f9f43d2a59c (diff)
dt-bindings: display: tegra: Add source clock for SOR
The SOR clock can have various sources, with the most commonly used being the sor_safe, pll_d2_out0, pll_dp and sor_brick clocks. These are configured using a three level mux, of which the first 2 levels can be treated as one. The direct parents of the SOR clock are the sor_safe, sor_brick and sor_src clocks, whereas the pll_d2_out0 and pll_dp clocks can be selected as parents of the sor_src clock via a second mux. Previous generations of Tegra have only supported eDP and LVDS with the SOR, where LVDS was never used on publicly available hardware. Clocking for this only ever required the first level mux (to select between sor_safe and sor_brick). Tegra210 has a new revision of the SOR that supports HDMI and hence needs to support the second level mux to allow selecting pll_d2_out0 as the SOR clock's parent. This second mux is knows as sor_src, and operating system software needs a reference to it in order to select the proper parent. Signed-off-by: Thierry Reding <treding@nvidia.com>
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