Merge branch 'cpsw-cpdma-DDR'

Grygorii Strashko says:

====================
net: ethernet: ti: cpsw: support placing CPDMA descriptors into DDR

This series intended to add support for placing CPDMA descriptors into
DDR by introducing new module parameter "descs_pool_size" to specify
size of descriptor's pool. The "descs_pool_size" defines total number
of CPDMA CPPI descriptors to be used for both ingress/egress packets
processing. If not specified - the default value 256 will be used
which will allow to place descriptor's pool into the internal CPPI
RAM.

In addition, added ability to re-split CPDMA pool of descriptors
between RX and TX path via ethtool '-G' command wich will allow to
configure and fix number of descriptors used by RX and TX path, which,
then, will be split between RX/TX channels proportionally depending on
number of RX/TX channels and its weight.

This allows significantly to reduce UDP packets drop rate for
bandwidth >301 Mbits/sec (am57x).

Before enabling this feature, the am437x SoC has to be fixed as it's
proved that it's not working when CPDMA descriptors placed in DDR.
So, the patch 1 fixes this issue.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

path: root/astraceroute/Makefile

astraceroute-libs =	-lGeoIP \
			-lpthread \
			-lz

astraceroute-objs =	xmalloc.o \
			ioops.o \
			proto_none.o \
			tprintf.o \
			bpf.o \
			str.o \
			sig.o \
			sock.o \
			link.o \
			dev.o \
			geoip.o \
			ring_rx.o \
			ring.o \
			astraceroute.o