summaryrefslogtreecommitdiff
path: root/list.h
blob: a8ac408e94689aefb88b38c69f47bd882474bec9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
#ifndef LIST_I_H
#define LIST_I_H

#include <urcu/list.h>
#include <urcu/rculist.h>

#define list_head	cds_list_head

#define LIST_HEAD	CDS_LIST_HEAD
#define INIT_LIST_HEAD	CDS_INIT_LIST_HEAD
#define LIST_HEAD_INIT	CDS_LIST_HEAD_INIT

#define list_add			cds_list_add
#define list_add_tail			cds_list_add_tail
#define list_del			cds_list_del
#define list_del_init			cds_list_del_init
#define list_move			cds_list_move
#define list_replace			cds_list_replace
#define list_splice			cds_list_splice
#define list_entry			cds_list_entry
#define list_first_entry		cds_list_first_entry
#define list_for_each			cds_list_for_each
#define list_for_each_safe		cds_list_for_each_safe
#define list_for_each_prev		cds_list_for_each_prev
#define list_for_each_prev_safe		cds_list_for_each_prev_safe
#define list_for_each_entry		cds_list_for_each_entry
#define list_for_each_entry_safe	cds_list_for_each_entry_safe
#define list_for_each_entry_reverse	cds_list_for_each_entry_reverse
#define list_empty			cds_list_empty
#define list_replace_init		cds_list_replace_init

#define list_add_rcu			cds_list_add_rcu
#define list_add_tail_rcu		cds_list_add_tail_rcu
#define list_replace_rcu		cds_list_replace_rcu
#define list_del_rcu			cds_list_del_rcu
#define list_for_each_rcu		cds_list_for_each_rcu
#define list_for_each_entry_rcu		cds_list_for_each_entry_rcu

#endif /* LIST_I_H */
mmit-subject'>cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'net/mpls')