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/*
 * netsniff-ng - the packet sniffing beast
 * Copyright (C) 2009, 2010 Daniel Borkmann
 * Copyright (C) 2012 Christoph Jaeger <christoph@netsniff-ng.org>
 * Subject to the GPL, version 2.
 */

#ifndef PROTO_H
#define PROTO_H

#include <ctype.h>
#include <stdint.h>

#include "hash.h"
#include "tprintf.h"

struct pkt_buff;

struct protocol {
	/* Needs to be filled out by user */
	unsigned int key;
	void (*print_full)(struct pkt_buff *pkt);
	void (*print_less)(struct pkt_buff *pkt);
	/* Used by program logic */
	struct protocol *next;
	void (*process)   (struct pkt_buff *pkt);
};

extern void empty(struct pkt_buff *pkt);
extern void hex(struct pkt_buff *pkt);
extern void ascii(struct pkt_buff *pkt);
extern void hex_ascii(struct pkt_buff *pkt);

#endif /* PROTO_H */
xt.git/diff/?h=nds-private-remove&id=73aaf15849d9421fa696c3d7785952d8100042b2&id2=66b8053e249c76b0d800805dac7e7dc80c3d7764'>diff)
spi: fsl-espi: fix support for all available clock rates
According to NXP ESPI datasheet, the SPI clock rate is: spi_clk = System_Clock / ( 2 * DIV16 * ( 1 + PM ) ) Where System_Clock is the platform clock divided by 2, DIV16 may be 1 or 16, and PM is a 4 bits integer (0 to 15). Isolating PM on the expression, we get: PM = (System_Clock / ( 2 * DIV16 * spi_clk ) ) - 1 Where System_Clock = mpc8xxx_spi->spibrg / 2, spi_clk = hz, and DIV16 = 1 or DIV16 = 16. So, PM = (mpc8xxx_spi->spibrg / ( 4 * hz) ) - 1 or PM = (mpc8xxx_spi->spibrg / ( 16 * 4 * hz) ) - 1 Current spi-fsl-espi driver can't configure the HW for all supported clock rates. It filters out clock rates for PM = 0 and PM = 1. This patch allows all range of supported clock rates to be configured on the ESPI controller. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat
-rw-r--r--drivers/spi/spi-fsl-espi.c28
1 files changed, 12 insertions, 16 deletions
diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c