/* * Copyright (C) 2010 Tobias Klauser * Copyright (C) 2010 chysun2000@gmail.com * * This file is part of nios2sim-ng. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ #ifndef _NIOS2_H_ #define _NIOS2_H_ #include "instruction.h" #include "memory.h" #define NIOS2_GP_REG_COUNT 32 /* there are really 32, but 16-31 are reserved for future use */ #define NIOS2_CTRL_REG_COUNT 16 struct tlb_entry; struct nios2 { /* General-Purpose Registers */ uint32_t gp_regs[NIOS2_GP_REG_COUNT]; /* Control Registers */ uint32_t ctrl_regs[NIOS2_CTRL_REG_COUNT]; /* Program counter */ uint32_t pc; /* User or Supervisor mode */ unsigned int mode; /* Exception cause */ unsigned int exception_cause; /* Configurable processor features */ bool has_mul; /* mul, muli */ bool has_mulx; /* mulxss, mulxsu, mulxuu */ bool has_div; /* div, divu */ bool has_mmu; /* Memory Management Unit */ /* struct tlb_entry tlb[TLB_NUM_LINES][TLB_NUM_WAYS]; */ struct memory *mem; /* Exception handler address */ uint32_t exception_handler_addr; }; /* processor modes */ enum { NIOS2_SUPERVISOR_MODE, NIOS2_USER_MODE, /* only used with MMU */ }; /* Aliases for general-purpose registers */ enum { zero = 0, at, et = 24, bt, gp, sp, fp, ea, ba, ra, }; /* Aliases for control registers */ enum { status = 0, estatus, bstatus, ienable, ipending, cpuid, /* reserved */ exception = 7, pteaddr, tlbacc, tlbmisc, /* reserved */ badaddr = 12, config, mpubase, mpuacc, }; /* status register fields */ #define NIOS2_STATUS_PIE_MASK 0x00000001 #define NIOS2_STATUS_U_MASK 0x00000002 #define NIOS2_STATUS_EH_MASK 0x00000004 /* exception register fields */ #define NIOS2_EXCEPTION_CAUSE_MASK 0x0000007C #define NIOS2_EXCEPTION_CAUSE_OFF 2 /* exception causes */ #define NIOS2_EX_RESET 0 #define NIOS2_EX_PROC_ONLY_RESET 1 #define NIOS2_EX_IRQ 2 #define NIOS2_EX_TRAP 3 #define NIOS2_EX_UNIMPLEMENTED 4 #define NIOS2_EX_DIV_ERR 8 #define NIOS2_EX_SUPERVISOR_ONLY_I 9 #define NIOS2_EX_SUPERVISOR_ONLY_D 11 #define NIOS2_EX_FAST_TLB_MISS 12 #define NIOS2_EX_NONE 255 /* pteaddr register fields */ #define NIOS2_PTEADDR_VPN_SHIFT 2 #define NIOS2_PTEADDR_VPN_MASK 0x007FFFFC #define NIOS2_PTEADDR_PTBASE_SHIFT 22 #define NIOS2_PTEADDR_PTBASE_MASK 0xFFC00000 /* tlbacc register fields */ #define NIOS2_TLBACC_PFN_MASK 0x000FFFFF #define NIOS2_TLBACC_G_MASK 0x00100000 #define NIOS2_TLBACC_X_MASK 0x00200000 #define NIOS2_TLBACC_W_MASK 0x00400000 #define NIOS2_TLBACC_R_MASK 0x00800000 #define NIOS2_TLBACC_C_MASK 0x01000000 /* tlbmisc register fields */ #define NIOS2_TLBMISC_D_MASK 0x00000001 #define NIOS2_TLBMISC_PERM_MASK 0x00000002 #define NIOS2_TLBMISC_BAD_MASK 0x00000004 #define NIOS2_TLBMISC_DBL_MASK 0x00000008 #define NIOS2_TLBMISC_PID_MASK 0x0007FFF0 #define NIOS2_TLBMISC_PID_OFF 4 #define NIOS2_TLBMISC_WE_MASK 0x00040000 #define NIOS2_TLBMISC_RD_MASK 0x00080000 #define NIOS2_TLBMISC_WAY_MASK 0x0007FFF0 #define NIOS2_TLBMISC_WAY_OFF 20 /* MMU-specific stuff */ #define TLB_NUM_ENTRIES 256 #define TLB_NUM_WAYS 16 #define TLB_NUM_LINES (TLB_NUM_ENTRIES / TLB_NUM_WAYS) struct tlb_entry { /* TLB Tag Portion */ uint32_t vpn; uint16_t pid; uint8_t g; /* TLB Data Portion Contents */ uint32_t pfn; uint8_t c; uint8_t r; uint8_t w; uint8_t x; /* TLB Data */ uint32_t buffer; }; extern void nios2_cpu_reset(struct nios2 *cpu); extern void nios2_cpu_init(struct nios2 *cpu); extern void nios2_simulate(struct nios2 *cpu); extern void nios2_cpu_inc_pc(struct nios2 *cpu); extern bool nios2_in_user_mode(struct nios2 *cpu); extern bool nios2_in_supervisor_mode(struct nios2 *cpu); extern void nios2_handle_exception(struct nios2 *cpu); extern uint32_t nios2_fetch_instr(struct nios2 *cpu); extern int nios2_execute_instr(struct nios2 *cpu, uint32_t instr); extern int nios2_load(struct nios2 *cpu, uint32_t addr, void *data, size_t size); extern int nios2_store(struct nios2 *cpu, uint32_t addr, void *data, size_t size); extern void nios2_dump_registers(struct nios2 *cpu); #endif /* _NIOS2_H_ */